Flexible imbedded test system for VLSI circuits

A test system for VLSI circuits having embedded test devices comprising:

• A VLSI logic chip having input means and output means,
• a plurality of separate combinational logic elements arranged sequentially in ranks on said chip between said input means and said output means and constituting as a whole the desired logic function of the chip,
• a plurality of flip-flop means arranged in ranks sequentially connected between said ranks of combinational logic elements and each having two independent data paths, a first data path being connected from a firs input connected with the output of a preceding combinational logic element and the second input being connected to receive the input of a preceding combinational logic element, a first output of said flip-flop being connected to a succeeding combinational logic element and a second output of said flip-flop being available for connection to a succeeding rank of flip-flops which succeeds the adjacent rank of combinational logic elements,
• control means on said chip for controlling each rank of flip-flops to operate either in a normal operation mode in which the first data input is selected to provide a data input to said flip-flop from a preceding combinational logic element or from a preceding rank of flip-flops.

A flip-flop comprising:

• first transmission gate means connected in a data path from a data input to said flip-flop,
• second transmission gate means connected in a testability input data path to said flip-flop,
• normal operation gate means for controlling said first and second transmission gate means to control which of said input data paths are provided as the output of said flip-flop,
• clock signal control means for controlling the timing of the output of data in said output data path,
• clock enable input means for controlling the enabling of input data in said first data input path to said flip-flop,
• SET and RESET control means for said flip-flop for controlling the output of said flip-flop to be a predetermined quantity regardless of the input signal on either of said first or second data input paths, and
• two separate isolated data output paths from said flip-flop.

A test system for VLSI circuits having embedded test devices comprising:

• A VLSI logic chip having inpuh means and output means,
• a plurality of separate combinational logic elements arranged sequentially in ranks on said chip between said input means and said output means and constituting as a whole the desired logic function of the chip,
• a plurality of flip-flop means arranged in ranks sequentially connected between said ranks of combinational logic elements and each having two independent data paths, the first data path being connected from a first input connected with the output of a preceding combinational logic element and a second input being connected to receive the input of a preceding combinational logic element, said flip-flop having at least one data output path,
• control means on said chip for controlling each rank of flip-flops to operate either in a normal operation mode in which the first data input is selected to provide a data input to said flip-flop from a preceding combinational logic element or from a preceding rank of flip-flops.

In an integrated circuit having:

• a plurality of input pins, a set of specialized combinational logic units comprising a plurality of flip flops and combinational logic wherein said flip flops have a conventional data input and an output which is connected as an input to said combinational logic, an on chip maintenance test system having an input register/random number generator and switching means for selectively connecting the combinational logic unit between a set of the input pins or the input register;
• wherein said integrated circuit has:
• specialized flip flops being operable in either a test mode or a normal operating mode, and wherein said flip flops have a test data input and a test data output which operate in said test mode, and having a mode select input to select which mode is enabled;
• wherein said specialized flip flops are so arranged and disposed to form a plurality of logic chains with the test data output of one specialized flip flop in such chain connected to the test data input of the next in such chain, and wherein said test data outputs of each preceding flip flop in the chain is connected to the test data input of each subsequent flip flop in the chain, and having switching means for selectively connecting the conventional data input to said specialized flip flops from an input pin or from the input register.

In a VLSI circuit having combinational logic, input pin means, and output pin means;

• an on-chip maintenance test system comprising:
• a control register having a plurality of outputs and having an input connected to an input pin,
• an input register having pseudo-random number generating capabilities connected to said control register for input and having a plurality of outputs,
• a set of memory elements having data and test inputs selectably enabled by a third input, and having at least one output, wherein the data and test inputs are selectably connected to receive output from said combinational logic or to receive output from another of said memory elements,
• an output register connected in series to said input register and in parallel to said output pin means,
• a first set of multiplexor means one of which has a first input connected to an off-chip test data input pin and the rest of which receive their first input from said memory element outputs, all of which also have a second input and an output connected to the test input of said set of memory elements,
• first switching means for selectively connecting said second input of said first set of multiplexor means between a set of said input pins and said input register.

In a VLSI circuit having combinational logic, input pin means, and output pin means;

• an on-chip maintenance test system comprising:
• a control register having a plurality of outputs and having an input connected to an input pin,
• an input register having pseudo-random number generating capabilities connected to said control register for input and having a plurality of outputs,
• a set of memory elements having an input and an output,
• a set of two to one multiplexors having a test data input and a data input and having an output, each said output being connected to the input of one of said set of memory elements, for selectably connecting said memory element between output from said combinational logic or output from another memory element,
• a set of four to one multiplexors connected to receive NOP and SSM signals as control inputs and having inputs to receive initialization, test data input, first switching means output, and output from either combinational logic or from a memory element, one of said four to one multiplexors receiving its test data input from the test data input pin means, and
• first switching means for selectively connecting said first switching means output between a set of
• said input pin means and said input register.