Floating point microprocessor with directable two level microinstructions
AssigneeFairchild Semiconductor Corporation
InventorsTich T. Dao, Gary R. Burke
Life of this patent
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Abstract
A microprocessor integrator circuit includes split nanocode memories which enables simultaneous execution of an arithmetic operation and an operand fetch for maximizing through-put. The circuit also includes a shared sequencing arithmetic logic unit which handles all microcode sequencing plus memory address sequencing. The circuit also provides nanocode sequencing which enables storage of constants and data in a microcode space which can include an off-chip writable control store. In addition, two level microcode is utilized to enable long routines to be vertically encoded without the overhead of a large number of read only memory outputs.
Claims7
A microprocessor comprising:
- (a) an instruction sequence register having an instruction address and connected to provide said instruction address to means for storing a first level of instruction;
- (b) a first level instruction register connected to receive a first level instruction from said first level instruction storage means;
- (c) means for storing a second level of instructions connected to receive an address from said first level instruction register, said second level instruction storage means comprising:
- (i) first means for storing a first portion of said second level instruction;
- and
- (ii) separate second means for storing a second portion of said second level instructions,
- (d) a first, second level instruction register connected to receive said first portion of said second level instruction;
- and,
- (e) a second, second level instruction register connected to receive said second portion of said second level instructions, wherein said first and second, second level instruction registers are connected to supply instruction portions to said first means for storing a first portion of said second level instructions and said separate second means for storing a second portion of said second level instructions respectively and at least a portion of instructions output from said first, second level instruction register is coupled to an input of said instruction sequence register through branch control means.
Dependencies are inferred from the claim text.