Method of making high breakdown voltage semiconductor device
AssigneeGeneral Electric Company
InventorsStephen D. Arthur, Victor A. K. Temple
Life of this patent
Estimating the term…
Abstract
A semiconductor device having at least one P-N junction and a multiple-zone junction termination extension (JTE) region which uniformly merges with the reverse blocking junction is disclosed. The blocking junction is graded into multiple zones of lower concentration dopant adjacent termination to facilitate merging of the JTE to the blocking junction and placing of the JTE at or near the high field point of the blocking junction. Preferably, the JTE region substantially overlaps the graded blocking junction region. A novel device fabrication method is also provided which eliminates the prior art step of separately diffusing the JTE region.
Claims13
A process of fabricating a semiconductor device including, when complete, at least one P-N junction, a first region of semiconductor material of one conductivity type having an upper surface and forming one side of said junction, a second region of semiconductor material having a lower surface and forming the other side of said junction, said second region being formed within said first region with conductivity type opposite that of the first region;
- and wherein said P-N junction includes a terminated portion at said upper surface of said first region, said second region includes a graded region adjacent to termination of said P-N junction, and said first region at a location beneath said P-N junction contains a depletion region width W.sub.D when said junction is reverse-biased to its ideal breakdown voltage, the improvement comprising, in combination with the foregoing:
- (a) forming a first mask of not so uniform thickness on said semiconductor device adjacent to said terminated portion to be used in forming a junction termination extension region, said step of forming a first mask comprising configuring said mask to expose a percentage x of a first portion of said first region adjacent said terminated portion and to expose a percentage y of a second portion of said first region adjacent said first portion remote from said terminated portion of said P-N junction, and wherein x is greater than y and adjacent openings in said first mask have a center-to center spacing of less than 0.25W.sub.D;
- (b) simultaneously doping said first and second portions of said first region through said first mask with the same concentration of dopant to form in said first region, a first zone contiguous with said terminated portion and a second zone adjacent said first zone, said first and second zones being of approximately the same depth and establishing a junction termination extension;
- (c) forming a second mask of not so uniform thickness on said semiconductor device adjacent said terminated portion and remote from the balance of said junction termination extension region, to be used in forming said second region including said graded region, said step of forming a second mask comprising configuring said mask to expose a percentage m of a first portion of said first region adjacent said terminated portion and to expose a percentage n of a second portion of said first region adjacent said first portion remote from said terminated portion of said P-N junction and wherein n is greater than m;
- (d) simultaneously doping said first and second portions of said first region through said second mask with the same concentration of dopant to form in said first region said second region such that said second region has a first zone contiguous with said terminated portion and a second zone adjacent said first zone;
- and
- (e) simultaneously diffusing said junction termination extension implant and said second region dopant implant, whereby the junction termination extension region is diffused with no additional diffusion time other than that required for diffusion of the P-N junction.
Dependencies are inferred from the claim text.