Streamlined instruction processor

An apparatus for processing data in response to a program composed of prespecified instructions in pipeline cycles, the data being stored in locations in a data memory addressed by data addresses and instructions being stored in locations in an instruction memory addressed by instruction addresses, and wherein instructions include file address field identifying sources of operand data and destinations for result data, the apparatus comprising:

• channel means for transferring addresses and data to the instruction and data memories (14,15,16) and for receiving data and instructions from the data and instruction memories, including an instruction interface (20) adapted for receiving instructions from the instruction memory, a data interface (22) adapted for communicating data between the apparatus and the data memory, and an address interface (21) adapted for supplying data addresses to the data memory and instruction addresses to the instruction memory;
• program addressing means (31), responsive to the program, for supplying a sequential instruction address or a non-sequential instruction address for an instruction to be executed according to the program;
• buffering means (26), coupled to receive instructions from the instruction interface and to the program addressing means, for buffering a sequence of instructions supplied to the instruction interface in buffer locations accessible in response to the sequential instruction address supplied by the program addressing means;
• caching means (29) coupled to the program addressing means, for storing sets of instructions in blocks of cache locations identified by a field in the instruction addresses and accessible in response to the non-sequential instruction address supplied by the program addressing means, the sets including instructions retrieved from sequential locations in the instruction memory, and a first instruction in each set being a target instruction of a non-sequential instruction address;
• instruction register means (27), coupled to buffering means and the caching means, for staging under program control an instruction accessed from the buffering means or the caching means in response to the sequential or non-sequential instruction address, respectively, supplied by the program addressing means;
• storage means (40) for storing data in a file of data locations identified by file addresses, the storage means including at least two read ports (A,B) and at least one write port (C), the read ports including means connected to receive file addresses in pipeline cycles for supplying data at the read port from data locations identified by the received file addresses, and the write port connected to receive data and including means connected to receive file addresses in pipeline cycles for writing data received at the write port to data locations identified by the received file addresses;
• file addressing means (43), coupled to receive file address field of the instructions staged from the instruction register means and to the storage means, for supplying file addresses identified by the file address field to the read ports and the write port under program control;
• executing means (42), responsive to the instructions staged from the instruction register means in pipeline cycles and coupled to the read ports, for executing the instructions and generating resulting data;
• result register means (53), coupled to supply data to the write port and connected to the executing means, for staging the resulting data.