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US 4,920,483 AGranted
A computer memory for accessing any word-sized group of contiguous bits
AssigneeData General Corporation
InventorsMichael A. Pogue, Morgan J. Dempsey, Shreyaunsh R. Shah, Leo C. Waible, III
Life of this patent
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Abstract
A memory for use in a digital data system stores n-bit words, and provides for accessing any group of n contiguous bits, regardless of whether aligned on an n-bit boundary. Barrel shifters facilitate rotating the retrieved bits so as to align them as convenient.
Claims6
A method of operating a memory in a digital data system,
- the memory being used for addressably storing and retrieving any of a plurality of n-bit words,
- the memory comprising a plurality of storage chips organized such that:
- (a) each storage chip stores bits associated with only one bit position of the n-bit words;
- and
- (b) each combination of address bits elicits a single bit from each of n storage chips, each containing a different bit position of the n-bit word,
- the digital data system including means for decrementing addresses by one;
- the method of comprising the steps of:
- (a) determining for each memory access an n-bit number "m" denoting a bit position offset within a n-bit word of the rightmost bit of a desired group of n contiguous bits;
- (b) using, for all chips storing bits of bit position equal to or less than m, the undecremented address;
- and
- (c) using, for all chips storing bits of bit position greater than m, the decremented address,
- whereby any n contiguous bits may be accessed.
9 more elements
A method of operating a memory in a digital data system,
- the memory being for addressably storing and retrieving any of a plurality of n-bit words,
- the memory comprising a plurality of storage chips organized such that:
- (a) each storage chip stores bits associated with only one bit position of the n-bit words;
- (b) each combination of address bits elicits a single bit from each of n storage chips, each containing a different bit position of the n-bit word;
- and
- (c) each storage chip is responsive to an address strobe signal in order for the chip to receive address bits,
- the digital data system including:
- (a) means for decrementing addresses by one;
- (b) means for providing a first address strobe signal before an address has been decremented;
- and
- (c) means for providing a second address strobe signal after an address has been decremented,
- the method comprising the steps of:
- (a) providing for each memory access an n-bit number "m" denoting a bit position offset within the n-bit word of the rightmost bit of a desired group of n contiguous bits;
- (b) for all chips storing bits of bit position equal to or less than m, strobing in the undecremented address with the first address strobe signal;
- and
- (c) for all chips storing bits of bit position greater than m, strobing in the decremented address with the second address strobe signal,
- whereby any n contiguous bits may be accessed.
14 more elements
A video digital data system including a three-dimensional memory,
- the three-dimensional memory being used for addressably storing a plurality of m-bit pixel representations,
- the three-dimensional memory being organized as m two-dimensional memories, each for addressably storing a plurality of n-bit words
- all of the m two-dimensional memories receiving the same addressing information,
- an m-bit pixel representation consisting of one bit stored in a corresponding position of each of the m two-dimensional memories,
- whereby an access of the three-dimensional memory at a particular address accesses n m-bit pixel representations.
2 more elements
Dependencies are inferred from the claim text.