Virtual address table look aside buffer miss recovery method and apparatus

In a data processor having

• a central processing unit, and
• at least one pipelined memory controller circuitry responsive to the central processing unit and having a memory pipeline, said central processing unit addressing data using a virtual address memory table look aside buffer, miss recovery circuitry comprising
• a virtual address first in-first out buffer means for storing virtual address data from the central processing unit during at least each memory access instruction,
• an instruction status first in-first out buffer means for storing instruction status data generated in the memory circuitry during at least each memory access instruction,
• means for detecting a memory access error condition during execution of a memory access instruction in the memory circuitry, and
• a resequencing means having
• means responsive to detection of the memory access error condition for at least correcting said memory access error condition, and
• means for replaying, in sequence, after said error is corrected, the instruction causing the error condition and those instructions entering and in the memory pipeline after the instruction causing the error condition, said replaying means being responsive to the virtual address and instruction status first in-first out buffer means for replaying said instructions.