One transistor memory cell with programmable capacitance divider

A memory array comprising:

• a plurality of bit lines defining columns;
• a plurality of word lines defining rows orthogonal to said bit lines;
• a plurality of memory cells located at crossings of word lines and bit lines, each memory cell comprising
• (a) a ferroelectric capacitance divider formed by two ferroelectric capacitors coupled together to have a common node and two poles, and (b) a switching device coupling said common node to said bit line, said switching device being responsively coupled to said word line at said crossing;
• a plurality of pairs of conductive common lines, one pair corresponding to each said word line, one of said common lines in the pair being coupled to said first poles in said memory cells along the row, and the other of said common lines of the pair being coupled to said second poles in the memory cells along the row, whereby distinct voltages can be applied to the first and second poles separately along a selected row;
• a voltage generator providing a first variable output and a second variable output, said first output being coupled to one of the conductive common lines in a pair, the second output being coupled to the other conductive common line of the pair;
• the remanent polarizations of said ferroelectric capacitors indicating the nonvolatile stored data.

A memory array comprising:

• a plurality of bit lines defining columns;
• a plurality of word lines defining rows orthogonal to said bit lines;
• a plurality of memory cells located at crossings of word lines and bit lines,
• each memory cell comprising (a) a ferroelectric capacitance divider formed by two capacitors coupled together to have a common node and two poles, and including ferroelectric material therein, and (b) a switching device coupling said common node to said bit line, said switching device being responsively coupled to said word line at said crossing;
• a plurality of pairs of conductive common lines, one pair corresponding to each said word line, one of said common lines in the pair being coupled to said first poles in said memory cells along the row, and the other of said common lines of the pair being coupled to said second poles in the memory cells along the row, whereby distinct voltages can be applied to the first and second poles separately along a selected row;
• a voltage generator providing a first variable output and a second variable output, said first output being coupled to one of the conductive common lines in a pair, the second output being coupled to the other conductive common line of the pair;
• the remanant polarizations of said ferroelectric material in said ferroelectric dividers indicating the nonvolatile stored data.