Semiconductor integrated circuit with self-testing

A semiconductor integrated circuit comprising:

• integrated circuit blocks connected in series for testing a system formed on said semiconductor integrated circuit, the system having a first stage and a following stage each including at least one of said integrated circuit blocks, each of said integrated circuit blocks comprising:
• logic means for carrying out a logic operation and providing output data signals corresponding thereto;
• an input terminal receiving input signals supplied to the integrated circuit blocks;
• pseudo-random pattern generating means for generating a pseudo-random pattern signal;
• data compressing means for receiving and compressing the output data signals supplied from said logic means to generate a compressed data signal;
• and
• an output terminal, operatively connected to said logic means, for receiving the output data signal from said logic means and for directly supplying the same to said input terminal of the integrated circuit blocks corresponding to the following stage,
• wherein at least one of said integrated circuit blocks of the first stage include first switching means for connecting said pseudo-random pattern generating means thereof to said logic means thereof during testing of the system, and
• wherein each of said integrated circuit blocks of the following stage include second switching means for connecting said input terminal thereof to said logic means thereof during testing of the system.