US 4,910,734 A · Intergrated circuit having testing function circuit and control circuit therefor

Abstract

A plurality of testing circuits formed of parallel registers are incorporated between a plurality of circuit portions constituting a data processing circuit. Each parallel register comprises scan latch circuits whose number corresponding to the number of sets of input and output terminals of the circuit portion. A first input terminal of each scan latch circuit is connected to an output terminal of the corresponding circuit portion, a second input terminal is connected to an input terminal of the corresponding circuit portion, an output terminal is connected to an input terminal of another circuit portion, respectively, control terminals of the scan latch circuits are connected together in each register to which a control signal is inputted. The testing circuit serves to test the circuit portion or operate the circuit portion upon reception the control signal corresponding to the test mode or the operation mode. The control signal is outputted by a control circuit having two input terminals, and it changes dependent on the combination of signals inputted to the input terminals.

Claims23

Dependent claims

A circuit having testing function, comprising:

a plurality of circuit portions constituting a data processing circuit having an operation mode and a test mode.
a plurality of testing means provided corresponding to said plurality of circuit portions, for making said plurality of circuit portions function as said data processing circuit in said operation mode and testing corresponding circuit portions independently in said test mode by concurrently bypassing at least another said circuit portion in said test mode;
and
control means applying control signals corresponding to said operation mode or said test mode to each of said plurality of testing circuits to activate said plurality of testing circuits.

1 more element

A circuit having testing function, comprising:

a plurality of circuit portions (1a.about.ma) constituting a data processing circuit having an operation mode and test mode;
a plurality of testing means (1.about.m) provided corresponding to said plurality of circuit portions, for making said plurality of circuit portions function as said data processing circuit in said operation mode and testing corresponding circuit portions independently in said test mode by bypassing at least one said circuit portion in said test mode;
and
control means (CNT) applying a first control signal corresponding to said operation mode to each of said plurality of testing circuits in accordance with a first input signal, and applying a second control signal corresponding to said test mode to each of said plurality of testing circuits in accordance with a second input signal, thereby activating said plurality of testing circuits.

1 more element

A plurality of testing circuits provided corresponding to a plurality of circuit portions constituting a data processing circuit having an operation mode and test mode, for independently testing corresponding circuit portions, each comprising:

connecting means (l.about.m) for connecting the corresponding circuit portion to another circuit portion, said connecting means making the connected circuit portions functions function as a portion of said data processing circuit in said operation mode and testing the corresponding circuit portion in said test mode by bypassing at least one said circuit portion in said test mode;
and
control means (c.sub.1 .about.c.sub.m) applying plural control signals respectively corresponding to said operation mode and said test mode to said connecting means to activate said connecting means.

Dependencies are inferred from the claim text.

Intergrated circuit having testing function circuit and control circuit therefor

Life of this patent

Intergrated circuit having testing function circuit and control circuit therefor

Life of this patent

Abstract

Claims23