Multiplexer diagnostic input patterns
AssigneeUnited Technologies Corporation
InventorJoseph F. Dechene
Life of this patent
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AssigneeUnited Technologies Corporation
InventorJoseph F. Dechene
Estimating the term…
Binary logic states (ONE, ZERO) are presented to the data inputs (24) of a multiplexer in a pattern characterized by a reversal of the binary logic states at input boundaries defined numerically as radix two raised to successive integer exponents. After sequencing the multiplexer address lines (22) to select the inputs to appear at the multiplexer output (25) in a desired sequence, the assembled output word (27) can, because of the pattern presented to the inputs, uniquely identify one of a number of particular address line conditions. Preselected codes are determined that facilitate identification of the conditions by comparing the codes to the output word in a flowchart of program steps (FIG. 4). Each code is associated with a pair of conditions, a first condition with a comparison result of all ONEs and a second with a comparison result of zero.
A method for testing a multiplex, comprising:
In a method for texting a multiplexer, which includes applying binary signals to inputs of said multiplexer, applying binary signals to address lines of said multiplexer in a desired address sequence to select the corresponding one of said binary signals on each of said inputs in a desired input sequence to appear at an output of said multiplexer, said desired input sequence beginning with a first input and ending with a last (Nth) input, assembling each said binary signal at said output during said desired input sequence into an N bit output word, and examining said N bit output word, the step of:
Dependencies are inferred from the claim text.