High input impedance, strobed CMOS differential sense amplifier

A CMOS sense amplifier circuit for sensing stored voltage differential between a first and second bit line, each bit line connected to a series of memory cells of a memory array, comprising:

• first and second voltage potential lines for providing first and second supply voltages;
• first and second sense nodes;
• first voltage node;
• a first input line connected to the first bit line for receiving input voltages from said first bit line;
• a second input line connected to the second bit line for receiving voltages from said second bit line;
• a first input transistor having a gate and a source-to-drain path, the gate of first input transistor connected to said first input line whereby input signals on the first input line controls the source-to-drain path of said first input transistor;
• a second input transistor having a gate and a source-to-drain path, the gate of second input transistor connected to said second input line whereby input signals on the second input line controls the source-to-drain path of said second input transistor;
• a first output line for carrying output voltages, said first output line connected to the first sense node on said sense amplifier;
• a second output line for carrying output voltages, said second output line connected to the second sense node on said sense amplifier;
• a primary CMOS pair of devices having a first upper transistor and a first lower transistor coupled in series by said first input transistor, each transistor having a gate and a source-to-drain path, the first upper transistor connected in series between said second voltage potential line and the first sense node, the first lower transistor connected in series between said first input transistor and the first voltage node;
• a secondary CMOS pair of devices having a second upper transistor and a second lower transistor coupled in series by said second input transistor, each transistor having a gate and a source-to-drain path, the second upper transistor connected between said second voltage potential line and the second sense node, the second lower transistor connected in series between said second input transistor and the first voltage node;
• the gate of said first upper transistor connected to both the gate of said first lower transistor and said second sense node;
• the gate of said second upper transistor connected to both the gate of said second lower transistor and said first sense node;
• second coupling means for coupling or decoupling said first voltage node to said first voltage potential line, said second coupling means including a first coupling transistor having a gate and a source-to-drain path, the first coupling transistor is an N-channel transistor connected in series between both the first and second lower transistors and said first voltage potential line;
• first coupling means for coupling or decoupling said first and second sense nodes to said second voltage potential line, said second coupling means comprising a second coupling transistor and a third coupling transistor, each second and third coupling transistor is a P-channel device having a gate and a source-to-drain path, the second coupling transistor is connected in parallel with the first upper transistor and the third coupling transistor connected in parallel with the second upper transistor, the gates of both the second and third coupling transistors are connected to the gate of said first coupling transistor;
• strobing means for simultaneously strobing the gates of said first coupling transistor, said second coupling transistor, and said third coupling transistor.

A CMOS sense amplifier circuit for sensing stored voltage differentials between a first and second bit line, each bit line connected to a series of memory cells of a memory array, comprising:

• first and second voltage potential lines for providing first and second supply voltages;
• first and second sense nodes;
• a first input line connected to the first bit line for receiving input voltages from said first bit line;
• a second input line connected to the second bit line for receiving voltages from said second bit line;
• a first input transistor having a gate and a source-to-drain path, the gate of first input transistor connected to said first input line whereby input signals on the first input line controls the source-to-drain path of said first input transistor;
• a second input transistor having a gate and a source-to-drain path, the gate of second input transistor connected to said second input line whereby input signals on the second input line controls the source-to-drain path of said second input transistor;
• a first output line for carrying output voltages, said first output line connected to the first sense node on said sense amplifier;
• a second output line for carrying output voltages, said second output line connected to the second sense node on said sense amplifier;
• a primary CMOS pair of devices having a first upper transistor and a first lower transistor connected in series, each transistor having a gate and a source-to-drain path, the first upper transistor connected in series between the first input transistor and said first lower transistor, the first lower transistor connected in series between the first upper transistor and said first voltage potential line, said first sense node connected between the first upper and the first lower transistor and within the source-to-drain path of said first upper and said first lower transistors;
• a secondary CMOS pair of devices having a second upper transistor and a second lower transistor connected in series, each transistor having a gate and a source-to-drain path, the second upper transistor connected in series between the first input transistor and said second lower transistor, the second lower transistor connected in series between the second upper transistor and said first voltage potential line, said second sense node connected between the second upper and the second lower transistor and within the source-to-drain path of said second upper and said second lower transistors;
• the gate of said first upper transistor connected to both the gate of said first lower transistor and said second sense node;
• the gate of said second upper transistor connected to both the gate of said second lower transistor and said first sense node;
• second coupling means for coupling or decoupling said CMOS sense amplifier circuit to said second voltage potential line, said second coupling means including a first coupling transistor having a gate and a source-to-drain path, the first coupling transistor is a P-channel transistor connected in series between both the first and second upper transistors and said second voltage potential line;
• first coupling means for coupling or decoupling said first and second sense nodes to said first voltage potential line, the first coupling means comprising a second coupling transistor and a third coupling transistor, each second and third coupling transistor is an N-channel device having a gate and a source-to-drain path, the second coupling transistor is connected in parallel with the first lower transistor and the third coupling transistor is connected in parallel with the second lower transistor, the gates of both the second and third coupling transistors are connected to the gate of said first coupling transistor;
• strobing means for simultaneously strobing the gates of said first coupling transistor, said second coupling transistor, and said third coupling transistor.

A sense amplifier for sensing and level shifting differential input voltages comprising:

• first and second voltage potential lines for providing first and second supply voltage;
• first and second sense nodes for providing differential output voltages;
• first voltage node;
• a pair of input lines for receiving said differential input voltages;
• a first pair of N-channel transistors, each transistor having a gate and conductive path, whereby the gates of the first pair of N-channel transistors are connected to respective ones of said pair of input lines;
• a cross coupled CMOS latch circuit including a second pair of N-channel transistors and a first pair of P-channel transistors, each transistor having a gate and conductive path, the conductive paths of the second pair of N-channel transistors coupled respectively between said first pair of N-channel transistors and said first voltage node, the conductive paths of the first pair of P-channel transistors coupled respectively between said first and second sense nodes and said second voltage potential line;
• first coupling means enabled by a strobe signal for coupling or decoupling said first and second sense nodes to said second voltage potential, the first coupling means including a second pair of P-channel transistor, each transistor having a gate and conductive path, the conductive path of said second pair of P-channel transistors respectively coupled between said first and second sense nodes and the second voltage potential line;
• second coupling means enabled by a strobe signal for coupling or decoupling said cross coupled CMOS latch circuit to said first voltage potential line, the second coupling means including an N-channel transistor having a gate and conductive path, the conductive path of said N-channel transistor coupled between said first voltage node and said first voltage potential line;
• and
• strobing means for strobing both the first coupling means and the second coupling means, wherein said strobing means includes a clocking input line coupled to both the gate of the N-channel transistor of said second coupling means and to the gates of the second pair of P-channel transistors of said first coupling means, such that said second coupling means and said first coupling means are clocked simultaneously, whereby the second coupling means is respectively enabled/disabled when the first coupling means is disabled enabled.