Bicmos read/write control and sensing circuit
AssigneeAdvanced Micro Devices, Inc.
InventorTzen-Wen Guo
Life of this patent
Estimating the term…
Abstract
A bipolar/CMOS read/write control and sensing circuit is provided for use with MOS memory cells in which data can be written into and sensed in the memory cells at high speeds. The MOS memory cell is coupled with a word line and between first and second bit lines at corresponding first and second sense nodes. The control and sensing circuit includes a bit-line clamping network which is responsive to an output control signal for clamping the first and second bit lines during a read operation so as to present a low impedance thereby decreasing the read time and for unclamping of the first and second bit lines during a write operation so as to present a high impedance which reduces the write time.
Claims19
A bipolar/CMOS read/write control and sensing circuit for use with MOS memory cells in which data can be written into and sensed in the memory cells at high speeds, said read/write control and sensing circuit comprising in combination:
- a MOS memory cell (22) being coupled with a word line and between first and second bit lines at corresponding first and second sense nodes;
- reading circuit means for detecting data signals stored in said memory cell and for amplifying the data signals to generate an output signal;
- said reading circuit means being formed of a bipolar differential pair of transistors (Q1, Q2), and an N-channel control transistor (N7), a well regulated current source (I.sub.R), and a cascode sensing circuit (40);
- one of said bipolar differential transistors (Q1) having its base connected to the first sense node and its emitter connected to the drain of said control transistor (N7), the other one of said bipolar differential transistors (Q2) having its base connected to the second sense node and its emitter connected to the drain of said control transistor (N7), the collectors of said bipolar differential transistors (Q1, Q2) being connected to said cascode sensing circuit (40), said control transistor (N7) having its gate connected to receive a column select signal, said current source (I.sub.R) being connected between the source of said control transistor (N7) and a lower supply potential;
- a writing circuit formed of first and second coupling transistors (N8, N9) each having source-to-drain conduction path electrodes and a gate, the source-to-drain electrodes of said first coupling transistor (N8) connecting a true data input signal to the first sense node, the source-to-drain electrodes of said second coupling transistor (N9) connecting a complemented data input signal to the second sense node;
- read/writing control means for generating an output control signal which has a first logic state for activating the gates of said first and second coupling transistors (N8, N9) during a write operation and has a second logic state for deactivating the gates of said first and second coupling transistors (N8, N9) during a read operation;
- bit-line current circuit means connected between said first and second bit lines for providing current on said first and second bit lines;
- and
- bit-line clamping means responsive to said output control signal for clamping of said first and second bit lines during the read operation so as to present a low impedance for a fast read and for unclamping of said first and second bit lines during the write operation so as to present a high impedance for a fast write.
A bipolar/CMOS read/write control and sensing circuit for use with MOS memory cells in which data can be written into and sensed in the memory cells at high speeds, said read/write control and sensing circuit comprising in combination:
- a MOS memory cell (22) being coupled with a word line and between first and second bit lines at corresponding first and second sense nodes;
- reading circuit means for detecting data signals stored in said memory cell and for amplifying the data signals to generate an output signal;
- a writing circuit formed of first and second coupling transistors (N8, N9) each having source-to-drain conduction path electrodes and a gate, the source-to-drain electrodes of said first coupling transistor (N8) connecting a true data input signal to the first sense node, the source-to-drain electrodes of said second coupling transistor (N9) connecting a complemented data input signal to the second sense node;
- read/writing control means for generating an output control signal which has a first logic state for activating the gates of said first and second coupling transistors (N8, N9) during a write operation and has a second logic state for deactivating the gates of said first and second coupling transistors (N8, N9) during a read operation;
- bit-line current circuit means connected between said first and second bit lines for providing current on said first and second bit lines;
- and
- bit-line clamping means responsive to said output control signal for clamping of said first and second bit lines during the read operation so as to present a low impedance for a fast read and for unclamping of said first and second bit lines during the write operation so as to present a high impedance for a fast write.
A bipolar/CMOS read/write control and sensing circuit for use with CMOS memory cells in which data can be written into and sensed in the memory cells at high speeds, said read/write control and sensing circuit comprising in combination:
- a MOS memory cell (22) being coupled with a word line and between first and second bit lines at corresponding first and second sense nodes;
- bit-line clamping means responsive to an output control signal for clamping of said first and second bit lines during a read operation so as to present a low impedance for a fast read and for unclamping of said first and second bit lines during a write operation so as to present a high impedance for a fast write;
- and
- said bit-line clamping means being formed of a CMOS inverter (I2) and a dual emitter bipolar transistor (Q3).
Dependencies are inferred from the claim text.