Dram with programmable capacitance divider

A dynamic RAM arrangement comprising a memory cell and a signal generator, the memory cell including first and second portions,

• the first portion comprising a volatile memory cell portion having a transistor coupled to a storage capacitor, and having an internal node between said storage capacitor and said transistor,
• said second portion being nonvolatile and comprising a capacitance divider formed by coupling first and second ferroelectric capacitors together to provide a common node coupled to plates of both of said ferroelectric capacitors and to provide first and second poles respectively coupled to the other two plates of said ferroelectric capacitors, the remanent polarization of the ferroelectric material in said ferroelectric capacitors representing the nonvolatile stored data,
• said common node in said second portion being coupled to said internal node in said first portion,
• said signal generator being coupled to provide a first variable signal (CLK3) and a second variable signal (CLK4) on first and second outputs, said first output being coupled to said first pole of said capacitance divider, said second output being coupled to said second pole of said capacitance divider.