Bit gating for efficient use of RAMs in variable plane displays

Apparatus for serializing 2.sup.M parallel outputs of an all points addressable memory into successive data groups, each data group corresponding to a respective value for a pixel in an image wherein the bit-length of the pixel value is selectable, the apparatus comprising:

• gate means, having (i) 2.sup.M parallel input junctions connected to the outputs of the memory and (ii) 2.sup.N output junctions, for selectively converting each set of 2.sup.M parallel inputs at said input junctions into 2.sup.M-n successive data groups, each data group having a bit-length of 2.sup.n of the 2.sup.N output junctions, wherein said gate means includes:
• a plurality of 2.sup.M-X parallel 2.sup.X -to-1 multiplexers positioned in a prescribed order, each having a set of 2.sup.X unique VD outputs as respective inputs thereto;
• means for selecting the qth input to each 2.sup.X -to-1 multiplexer as the output therefrom, where q is an integer 1.ltoreq.q.ltoreq.2.sup.X ;
• a plurality of 2-to-1 multiplexers, each receiving as the first input thereto the output from a respective 2.sup.X -to-1 multiplexer;
• and
• means for clocking data through the 2-to-1 multiplexers as parallel data bits in response to a clock pulse, the data bit from each 2-to-1 multiplexer being conveyed to a respective output junction SB(i) wherein the data bit at output junction SB(i) represents the second input to the 2-to-1 multiplexer associated with the lower-ordered output junction SB(i-1) where i is an integer greater than 0;
• wherein said signal input communicating means includes:
• means for selecting either the first input or the second input for all of the 2-to-1 multiplexers;
• and
• means for selecting predetermined output junctions as video outputs
• wherein the selection of output junctions depends on the number of bits to be allocated to each pixel;
• and
• means for communicating to said gate means a signal input which controls the bit-length 2.sup.n of data groups, wherein n is a selectable integer 1.ltoreq.n.ltoreq.N.ltoreq.M.

Apparatus for displaying image data comprising:

• video display;
• means for serializing parallel outputs VD(0) through VD(2.sup.M) (where M is an integer) of an all points addressable memory into successive data groups, each data group corresponding to a respective value for a pixel in an image wherein the bit-length of the pixel value is selectable, the serializing means comprising:
• gate means, having (i) 2.sup.M parallel input junctions connected to the outputs of the memory and (ii) 2.sup.N output junctions, for selectively converting each set of 2.sup.M parallel inputs at said input junctions into 2.sup.M-n successive data groups, each data group having a bit-length of 2.sup.n data bits, wherein each data group exits the gate means through 2.sup.n of the 2.sup.N output junctions;
• and
• means for communicating to said gate means a signal which controls the bit-length 2.sup.n of data groups, wherein n is a selectable integer 1.ltoreq.n.ltoreq.N.ltoreq.M;
• and
• control means for generating a pixel value signal for each data group exiting the gate means and entering the pixel value signals to the display in sequence, wherein said control means includes:
• palette memory means for associating each input address thereto with a color indicative value;
• address means for converting data group inputs into address inputs to said palette memory means;
• and
• masking means for selectively entering, as address means input, only data group data on the 2.sup.n of the 2.sup.N output junctions.