Apparatus for loading and verifying a control store memory of a central subsystem

In combination with a data processing system comprising plural functional units interconnected by means of a common system bus, said functional units comprising, in combination,

• at least first and second microprogrammed processors operating under the control of microinstructions stored in a single shred writable control store, said first and second processors having first and second ports respectively connecting said first and second processors to said system bus,
• a main memory unit,
• a peripheral storage means for storing microinstructions, and
• a supervisory processor for issuing commands via said system bus to specified ones of said functional units, apparatus for loading said control store with microinstruction stored in said peripheral storage means comprising, in combination,
• means in said supervisory processor for issuing commands to transfer said microinstructions from said peripheral storage means to said main memory unit,
• means in said supervisory process for issuing commands to transfer said microinstructions from said main memory unit to said control store via said first port,
• error detection means connected to said control store for transmitting a validity check signal to said supervisory processor to indicate whether said microinstruction have been correctly stored in said control store, and
• means in said supervisory processor responsive to said validity check signal for initiating normal processing if said microinstructions are correctly stored in the control store and for attempting to re-transfer said microinstructions from said main memory unit to said control store via said second port if said microinstructions were not correctly stored.