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US 4,910,664 AGranted
Data processor with apparatus for reducing loop processing time
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTakeshi Arizono
Life of this patent
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Abstract
A data processing system with an apparatus for reducing loop processing time including an address reset circuit that resets the program counter and prefetch counter to the loop beginning address when the program executes the instruction at the loop ending address. The need for repeated address calculation for branching to a loop beginning address after each loop execution cycle is eliminated, thereby speeding up the loop processing.
Claims6
A data processing system for decreasing loop processing time comprising:
- a prefetch counter indicating an address of an instruction to be prefetched;
- a program counter indicating an address of an instruction under execution;
- a loop-beginning address register for storing a beginning address of a loop portion of a program;
- a loop-end address register for storing an address after the completion of the loop;
- an execution unit for executing a while instruction for storing a loop-beginning address in the loop-beginning address register and storing the loop-end address in the loop-end address register, respectively, a continue instruction resetting said program counter to the contents of said loop-beginning address register, and a break instruction for resetting said program counter to the contents of said loop-end address register, and
- an address reset means coupled to the program counter and loop-end address register, for the address stored in the loop-beginning address register to the program counter when the coincidence an address stored in the program counter and the address stored in the loop-end address register is detected;
- and coupled to the prefetch counter and loop-end address register, for moving the address stored in the loop-beginning address register to the prefetch counter when the coincidence of the the address stored in the prefetch counter and the address stored in the loop-end address register is detected.
4 more elements
A data processing system for decreasing loop processing time comprising:
- a prefetch counter indicating an address of an instruction to be prefetched;
- a program counter indicating an address of an instruction under execution;
- a loop-beginning address register for storing a beginning address of a loop-portion of a program;
- a loop-end address register for storing an address after the completion of the loop;
- an address reset means coupled to the program counter and loop-end address register, for moving the address stored in the loop-beginning address register to the program counter when the coincidence of and address in the program counter and the address stored in the loop-end address register is detected, and also coupled to the prefetch counter and loop-end address register, and for moving the address stored in the loop-beginning address register to the prefetch counter when the coincidence of the address stored in of the prefetch counter and the address stored in the loop-end address register is detected.
2 more elements
Dependencies are inferred from the claim text.