Microprocessor providing bus access for unconditional instruction execution

Abstract

In a look-ahead control type of microprocessor, each area of a buffer memory temporarily stores a macroinstruction and a separate tag unit memory is provided for each such area, the tag being binary 1 when a macroinstruction is stored and binary 0 when an area becomes vacant. When one area becomes vacant because its macroinstruction is outputted to a decoder, the tag for that area provides a binary 0 to a NAND circuit which then outputs a binary 1 to one input of an AND gate. If the decoded macroinstruction is not an unconditional branch instruction, the decoder sets a flip-flop to provide a binary 1 to the other input of the AND gate so the AND gate will output a binary 1 to a bus access control logic circuit as a fetch demand signal so an external memory will provide a macroinstruction over an external data bus to the vacant buffer memory area. If the decoded macroinstruction is a unconditional branch instruction the decoder resets the flip-flop to provide a binary 0 to the AND gate which outputs a binary 0 so no fetch demand signal is provided. Thus, the external bus is not used to fetch a subsequent macroinstruction reducing the waiting time for the use of the bus for execution of unconditional branch instructions.

Dependencies are inferred from the claim text.