Apparatus for transferring signals and data under the control of a host computer

An apparatus for transferring signals and data, wherein the signals and data are transferred under the control of a host computer from the host computer to first and second peripheral devices and from the first and second peripheral devices to the host computer, wherein the signals and data are transferred over a bus coupling the first and second peripheral devices to the host computer, and wherein the bus is normally in a logical first state, comprising:

• means, coupled to the first peripheral device, containing a first hard-wired identification number as a first address of the first peripheral device;
• means, coupled to the second peripheral device, containing a second hard-wired identification number as a first address of the second peripheral device;
• means, coupled to the host computer, for generating a plurality of signals for transmission over the bus to at least one of the peripheral devices, wherein the plurality of signals comprise an attention signal, a synchronization signal, one of a plurality of commands, and a stop signal, wherein the plurality of signals allow the host computer to control at least one of the peripheral devices, and wherein each of the plurality of commands includes an address of at least one of the first and second peripheral devices to which the command is directed;
• means, coupled to the first peripheral device, for generating a first service request signal for transmission to the host computer by holding the bus at a logical second state for a period of time after transmission of the stop signal, wherein the first service request signal indicates to the host computer that at least one of the peripheral devices has data to send to the host computer and requests a command from the host computer that would permit the peripheral device to transmit the data to the host computer, and wherein the transmission of the first service request signal is selectively enabled and disabled by the host computer;
• means, coupled to the second peripheral device, for generating a second service request signal for transmission to the host computer by holding the bus at the logical second state for a period of time after transmission of the stop signal, wherein the second service request signal indicates to the host computer that at least one of the peripheral devices has data to send to the host computer and requests a command from the host computer that would permit the peripheral device to transmit the data to the host computer, and wherein the transmission of the service request signal is selectively enabled and disabled by the host computer;
• means, coupled to the host computer, for transmitting data from the host computer to at least one of the peripheral devices over the bus;
• means, coupled to the first peripheral device, for transmitting data over the bus to the host computer from the first peripheral device if and only if one of the plurality of commands received by the first peripheral device from the host computer is a command to transfer data from the first peripheral device to the host computer;
• means, coupled to the second peripheral device, for transmitting data over the bus to the host computer from the second peripheral device if and only if one of the plurality of commands received by the second peripheral device is a command to transfer data from the second peripheral device to the host computer;
• first collision sensing means, coupled to the first peripheral device, for setting a collision detect bit to the logical first state from the logical second state when the first peripheral device attempts to transmit data in the logical first state on the bus but the bus is in or goes to the logical second state, wherein the first peripheral device stops transmitting data after the collision detect bit is set to the logical first state, and wherein the first collision sensing means provides a control over access to the bus by the first peripheral device;
• second collision sensing means, coupled to the second peripheral device, for setting a collision detect bit to the logical first state from the logical second state when the second peripheral device attempts to transmit data in the logical first state on the bus but the bus is in or goes to the logical second state, wherein the second peripheral device stops transmitting data after the collision detect bit is set to the logical first state, and wherein the second collision sensing means provides a control over access to the bus by the second peripheral device;
• and
• means, coupled to the host computer, for storing (1) a first number at a first soft address location and (2 ) a second number at a second soft address location, wherein if a collision is detected and is the result of the first hard-wired identification number being the same as the second hard-wired identification number, then the host computer (1) sends the first number stored at the first soft address location as data over the bus to the first peripheral device for storage by the first peripheral device as a second address of the first peripheral device and (2) sends the second number stored at the second soft address location as data over the bus to the second peripheral device for storage by the second peripheral device as a second address of the second peripheral device, wherein the first number is different from the second number.