US 4,908,842 A · Flash synchronized gated sample clock generator

Abstract

Digital flash synchronization for instantaneously re-phasing an asynchronous clock signal with a second signal from a desired source is disclosed. Included is a delay line with a multiplicity of equally spaced taps for presenting a multiplicity of clock signals at different phases. A first register is included to receive the second signal as a trigger and to store a snap-shot of the clock signals from the taps of the delay line and the undelayed clock signal in response to the second signal. A look-up table is used to identify the phase of the clock to be selected that agrees most closely with the second signal from the snap-shot of signals stored in the first register. Next, a multiplexer is used to select the preliminary re-phased clock signal from the clock signal and each of the signals at the taps of the delay line in response to the identified phase from the look-up table. A delay is then provided to delay the second signal by the propagation delay of the look-up table and the multiplexer. This delay is followed by a second register that receives the delayed second signal and produces the delayed second signal in response to the preliminary re-phased clock signal. The delayed second signal from the second register and the preliminary re-phased clock signal from the multiplexer are applied to an OR gate to produce the final re-phased clock signal. Modifications of the basic embodiment are provided to handle a range of clock frequencies and to minimize the size of the delay line and the look-up table.

Claims20

Dependent claims

Digital flash synchronizer apparatus for instantaneously re-phasing an asynchronous clock signal at a first frequency with a selected characteristic of a second signal from a desired source at a second frequency, wherein said first frequency is higher than the second frequency, said apparatus comprising:

delay line means disposed to receive said clock signal and having a multiplicity of equally spaced taps for presenting a multiplicity of said clock signals at different phases, one with respect to the others;
first register means disposed to receive said second signal as a trigger and receives the clock signals from the taps of the delay line means for storing the signal levels of the clock signal and the signals at the taps of the delay line means in response to said second signal;
look-up table means connected to said first register means to receive the signal levels therefrom as the address to the table for identifying the phase of the clock to be selected that agrees most closely with the selected characteristic of said second signal;
multiplexer means coupled to receive said clock signal and each of the signals at the taps of said delay line means as input signals and the output signals from said look-up table means as the control input signals for selecting the preliminary re-phased clock signal from the input signals to said multiplexer means;
delay means for delaying said second signal by at least the total propagation delay of the look-up table means and the multiplexer means;
second register means coupled to receive the output signal from said delay means for producing said delayed second signal in response to said preliminary re-phased clock signal;
and
OR gate means coupled to receive at one input terminal the delayed second signal from said second register means and the preliminary re-phased clock signal from the multiplexer means for producing a final re-phased clock signal on the output terminal of said OR gate means.

5 more elements

Dependencies are inferred from the claim text.

Flash synchronized gated sample clock generator

Life of this patent

Flash synchronized gated sample clock generator

Life of this patent

Abstract

Claims20