US 4,908,796 A · Registered outputs for a memory device

Abstract

Registered output circuitry for a memory device includes a first latch which stores data from a sense amplifier on the rising edge, and outputs it on the falling edge, of the falling edge of an OE signal. This data stored in the latch is provided as output of only y, during the preceding rising edge of the OE signal the CE signal to the memory device was a logical 0 level, and the WE signal was a logical 1 level. Since the falling edge of the OE signal is the beginning of the memory cycle, the data at the output pin of the memory is the data read in the previous read cycle. This latency, however, enables a shortened average cycle time, and also provides registered outputs without the necessity of an external clock signal applied to the memory device.

Claims11

Dependent claims

A method for providing data at an output terminal of a memory device comprising the steps of:

(a) storing, in a storage device, the output signal of a sense amplifier in said memory device upon a first transition of an output enable signal applied to said memory device;
(b) receiving a chip enable signal provided externally to said memory device upon a second transition, opposite to said first transition of said output enable signal, and placing a first logic level on an internal node of said memory device if said chip enable signal is within a predetermined voltage range;
and
(c) enabling an output driver circuit, coupled to said storage device, to drive said output terminal of said memory device in response to data stored in said storage device if said internal node is at said first logic level.

1 more element

An integrated circuit memory, comprising:

terminals and at least one data terminal address;
at least two but no more than three terminals for incoming control signals, including an output enable signal terminal and a chip-enable signal connection;
an array of memory cells;
address decoding logic, connected to decode incoming address signals which may be received at said address connections and to access a selected one of said memory cells accordingly;
at least one sense amplifier, connected to amplify signals which may be read out from an accessed one of said cells;
and
an output driver circuit, operatively connected to amplify the data output of said sense amplifier, and to drive a data output, on at least one of said data connections, accordingly;
wherein, during a read operation,
when said output enable signal transitions from a second state to a first state, said output driver circuit;
ceases to drive said data output,
and also stores an instantaneous data state in accordance with the instantaneous output of said sense amplifier,
and also stores the instantaneous state of said chip-enable signal;
and, when said output enable signal transitions from said first state to said second state, said output driver circuit;
drives said data output in accordance with said stored instantaneous data state, but only if said stored instantaneous state of said chip-enable signal corresponds to a predetermined state.

11 more elements

Dependencies are inferred from the claim text.

Registered outputs for a memory device

Life of this patent

Registered outputs for a memory device

Life of this patent

Abstract

Claims11