US 4,908,795 A · Semiconductor integrated circuit device with built-in memories

Abstract

A data processing LSI constructing a microcomputer has an EPROM for changing a program. The EPROM can be accessed directly through the external terminals of the data processing LSI. The EPROM is statically operated when it is written with data by direct access. However, the statically operated EPROM consumes relatively high power. This power consumption by the EPROM is reduced by dynamically operating its read circuit, address decoder and so on. For example, the read circuit is constructed of a sense amplifier and a latch circuit, and the sense amplifier has its operation interrupted after the latch circuit has latched the read data. The address decoder is composed of a load MOSFET and address MOSFETs. The load MOSFET is caused to act as a precharge element in the dynamic operation and as an operation current feeding element in the static operation.

Claims36

Dependent claims

A semiconductor integrated circuit device comprising:

an information processing circuit which is operated by a periodic timing signal;
an electrically programmable read only memory which is coupled to said information processing circuit and which is accessed by either said information processing circuit to read out data stored therein or from outside of said semiconductor integrated circuit device to write data therein, wherein said electrically programmable read only memory has a memory array and a peripheral circuit and wherein said peripheral circuit is statically or dynamically operated to access said memory array when said electrically programmable read only memory is accessed by either said information processing circuit or from the outside of said semiconductor integrated circuit device;
and
a control circuit for setting an operation of said peripheral circuit of said electrically programmable read only memory so that said peripheral circuit is statically operated when said electrically programmable read only memory is accessed from the outside of said semiconductor integrated circuit device and said peripheral circuit is dynamically operated in response to said periodic timing signal when said electrically programmable read only memory is accessed by said information processing circuit.

1 more element

A single-chip microcomputer comprising:

a bus;
a central processing unit (CPU) which is operated by a periodic timing signal and which is coupled to said bus;
an electrically programmable read only memory which has address input terminals and data input/output terminals coupled to said bus and which is accessed by either said CPU or from outside of said single-chip microcomputer, wherein said electrically programmable read only memory has a memory array and a peripheral circuit to access said memory array;
a first external terminal which is coupled to said bus and to which an address signal to be fed to said electrically programmable read only memory is fed when said electrically programmable read only memory is accessed from the outside of said single-chip microcomputer;
a second external terminal which is coupled to said bus and to which data to be fed to said electrically programmable read only memory is fed when said electrically programmable read only memory is accessed from the outside of said single-chip microcomputer;
a third external terminal to which an indication signal for indicating whether said electrically programmable read only memory is accessed by said CPU or from the outside of said single-chip microcomputer is fed;
discriminator means responsive to said indication signal and for discriminating whether or not said indication signal is indicating that said electrically programmable read only memory is accessed from the outside of said single-chip microcomputer;
and
control means coupled to said peripheral circuit of electrically programmable read only memory and responsive to an output signal of said discriminator means and for setting an operation of said peripheral circuit of said electrically programmable read only memory so that said peripheral circuit is statically operated when said electrically programmable read only memory is accessed from the outside of said single-chip microcomputer and said peripheral circuit of said electrically programmable read only memory is dynamically operated in response to said periodic timing signal when said electrically programmable read only memory is accessed by said CPU.

6 more elements

A single-chip microcomputer comprising:

a bus;
a central processing unit (CPU) which is operated by a periodic timing signal and which is coupled to said bus;
an electrically programmable read only memory which has address input terminals and data input/output terminals coupled to said bus and which is accessed by either said CPU or from outside of said single-chip microcomputer, wherein said electrically programmable read only memory has a memory array and a peripheral circuit to access said memory array;
a first external terminal which is coupled to said bus and to which an address signal to be fed to said electrically programmable read only memory is fed when said electrically programmable read only memory is accessed from the outside of said single-chip microcomputer;
a second external terminal which is coupled to said bus and to which data to be fed to said electrically programmable read only memory is fed when said electrically programmable read only memory is accessed from the outside of said single-chip microcomputer;
discriminator means for discriminating whether or not said electrically programmable read only memory is accessed from the outside of said single-chip microcomputer;
and
control means coupled to said peripheral circuit of electrically programmable read only memory and responsive to an output signal of said discriminator means for setting an operation of said peripheral circuit of said electrically programmable read only memory so that said peripheral circuit is statically operated when said electrically programmable read only memory is accessed from the outside of said single-chip microcomputer and said peripheral circuit of said electrically programmable read only memory is dynamically operated in response to said periodic timing signal when said electrically programmable read only memory is accessed by said CPU.

5 more elements

A single-chip microcomputer comprising:

a bus;
a central processing unit (CPU) which is operated by a periodic timing signal and which is coupled to said bus;
an electrically programmable read only memory which has address input terminals and data input/output terminals coupled to said bus and which is accessed by either said CPU or from outside of said single-chip microcomputer, wherein said electrically programmable read only memory has a memory array and a peripheral circuit to access said memory array;
a first external terminal which is coupled to said bus and for transmitting an address signal from the outside of said single-chip microprocessor to said bus when said electrically programmable read only memory is accessed from the outside of said single-chip microcomputer;
a second external terminal which is coupled to said bus and to which data to be fed to said electrically programmable read only memory is fed when said electrically programmable read only memory is accessed by the outside of said single-chip microcomputer;
and
control means coupled to said peripheral circuit of said electrically programmable read only memory and for setting an operation of said peripheral circuit of said electrically programmable read only memory so that said peripheral circuit is statically operated when said electrically programmable read only memory is accessed from the outside of said single-chip microcomputer and said peripheral circuit of said electrically programmable read only memory is dynamically operated in response to said periodic timing signal when said electrically programmable read only memory is accessed by said CPU.

4 more elements

A one-chip microcomputer including an electrically programmable read only memory and a microprocessor which is coupled to said electrically programmable read only memory via a bus and which executes a predetermined data processing operation in accordance with a program stored in said electrically programmable read only memory in response to a periodic timing signal, wherein said electrically programmable read only memory includes a memory array and a peripheral circuit for accessing said memory array, said one-chip microcomputer comprising:

a first external terminal which is coupled to said bus and to which an address signal to be fed to said electrically read only memory is fed when said electrically read only memory is accessed from the outside of said one-chip microcomputer;
a second external terminal which is coupled to said bus and to which data constituting said program to be written into said electrically programmable read only memory is fed when said electrically programmable read only memory is accessed from the outside of said one-chip microcomputer;
discriminator means for discriminating whether or not said electrically programmable read only memory is accessed from the outside of said one-chip microcomputer;
and
control means coupled to said peripheral circuit and responsive to an output of said discriminator means and for controlling an operation of said peripheral circuit so that said peripheral circuit is statically operated when said electrically programmable read only memory is accessed from the outside of said one-chip microcomputer and said peripheral circuit of said electrically programmable read only memory is dynamically operated in response to said periodic timing signal when said electrically programmable read only memory is accessed by said microcomputer.

2 more elements

A one-chip microcomputer including an electrically programmable read only memory in which data constituting a program is written by writer means provided on the outside of said one-chip microcomputer and a microprocessor which is coupled to said electrically programmable read only memory via a bus and which executes a predetermined data processing operation in accordance with the program stored in said electrically programmable read only memory in response to a periodic timing signal, wherein said electrically programmable read only memory includes a memory array and a peripheral circuit for accessing said memory array, said one-chip microcomputer comprising:

a first external terminal which is coupled to said bus and to which an address signal to be fed to said electrically read only memory is fed when said electrically read only memory is accessed from the outside of said one-chip microcomputer;
a second external terminal which is coupled to said bus and to which data constituting said program to be written into said electrically programmable read only memory is fed when said electrically programmable read only memory is accessed from the outside of said one-chip microcomputer;
discriminator means for discriminating whether or not said electrically programmable read only memory is accessed from the outside of said one-chip microcomputer;
and
control means coupled to said peripheral circuit and responsive to an output of said discriminator means and for controlling an operation of said peripheral circuit so that said peripheral circuit is statically operated when said electrically programmable read only memory is accessed from the outside of said one-chip microcomputer and said peripheral circuit of said electrically programmable read only memory is dynamically operated in response to said periodic timing signal when said electrically programmable read only memory is accessed by said microcomputer.

2 more elements

A single-chip microcomputer including an electrically programmable read only memory in which data constituting a program is written by writer means provided on the outside of said single-chip microcomputer and a microprocessor which is coupled to said electrically programmable read only memory via a bus and which executes a predetermined data processing operation in accordance with the program stored in said electrically programmable read only memory in response to a periodic timing signal, wherein said electrically programmable read only memory includes a memory array and a peripheral circuit to access said memory array, and wherein said writer means provides a supply voltage to said electrically programmable read only memory, said single-chip microcomputer comprising:

a first external terminal coupled to said bus for transmitting an address signal from the writer means to said bus when said electrically read only memory is accessed by the writer means;
a second external terminal which is coupled to said bus and to which the data to be fed to said electrically programmable read only memory from the writer means is fed;
a third external terminal to which an indication signal for indicating whether said electrically programmable read only memory is accessed by said microprocessor or by the writer means is fed;
discriminator means responsive to said indication signal for discriminating whether or not said indication signal is indicating that said electrically programmable read only memory is accessed by the writer means;
and
control means coupled to said peripheral circuit of the electrically programmable read only memory and responsive to an output signal of said discriminator means for setting an operation of said peripheral circuit of said electrically programmable read only memory so that said peripheral circuit is statically operated when said electrically programmable read only memory is accessed by the writer means and said peripheral circuit of said electrically programmable read only memory is dynamically operated in response to said periodic timing signal when said electrically programmable read only memory is accessed by said microprocessor.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit device with built-in memories

Life of this patent

Semiconductor integrated circuit device with built-in memories

Life of this patent

Abstract

Claims36