Semiconductor memory device with improved output circuit
AssigneeNEC Corporation
InventorTakashi Yamaguchi
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Abstract
A semiconductor memory device according to the present invention has a memory cell array and an output circuit provided in association with a pair of data lines which comprises a series combination of a main sense amplifier circuit and a first NOR gate, a series combination of an auxiliary sense amplifier circuit and a second NOR gate, and an output inverter circuit, and the two series combinations produces a data bit signal and the inverse thereof for driving the output inverter circuit, so that a time period consumed for a read-out operation is constant regardless of the logic level of a data bit read out from the memory cell.
Claims5
A semiconductor memory device having a plurality of memory cells arranged in rows and columns, a data bit read out from one of said memory cells being supplied to a pair of data lines, comprising:
- (a) a first sense amplifier circuit coupled to said data lines and operative to increase a difference in voltage level between said data lines for producing a data bit signal;
- (b) a first NOR gate activated by an output enable signal and coupled at an input node thereof to said first sense amplifier circuit for producing an inverted signal of said data bit signal;
- (c) a second sense amplifier circuit coupled to said data lines and operative to increase the difference in voltage level on said data lines for producing the inverse of said data bit signal;
- (d) a second NOR gate activated by said output enable signal and coupled at an input node thereof to said second sense amplifier circuit for producing a non-inverted signal of said data bit signal;
- and
- (e) an output inverter circuit responsive to said inverted signal and said non-inverted signal for producing an output data signal.
Dependencies are inferred from the claim text.