Back to results
US 4,908,772 AGranted
Integrated circuits with component placement by rectilinear partitioning
AssigneeBell Telephone Laboratories, Incorporated
InventorMely C. Chi
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeBell Telephone Laboratories, Incorporated
InventorMely C. Chi
Estimating the term…
An integrated circuit, and a method for laying out and creating the integrated circuit, which contains large circuit blocks placed at any desired location on a chip, with the rest of the circuitry placed in the remaining non-rectangular area on the chip. The layout takes account of connections from within the circuit area to connection points external to the area. The procedure for the automatic layout proceeds in two steps. The first step is global partitioning and placement, and the second is detailed placement. The global partitioning performs the logical partitioning of the cells into clusters to be placed among and between the macro cells and the external terminals, with each cluster being eventually laid-out in a rectangular area. The second step involves the detailed placement of cells within the rectangular areas. Partitioning is accomplished by an iterative process, where at each iterative step the non-rectangular area is divided into two parts of approximately equal size. The circuitry to be placed in each of the divided areas is then partitioned in proportion to the size of the areas in accordance with known techniques, coupled with a novel terminal reassignment procedure.
An integrated circuit having a predetermined area for placing components (FIG. 3 101, 102) and further having input/output terminals (FIG. 3 104), macro cells situated in said area (FIG. 3 103), and a plurality of interconnected integrated circuit cells situated in said area and connected to said macro cells and to said input/output terminals, where said integrated circuit is made in accordance with a process COMPRISING:
A method for laying out integrated circuits comprising input ports, output ports, macro cells requiring rectilinear integrated circuit layout areas, and a plurality of integrated circuit cells within a predetermined area and in accordance with a procedure comprising the steps of:
A method for laying out integrated circuits comprising input ports, output ports, macro cells requiring rectilinear integrated circuit layout areas, and a plurality of integrated circuit cells within a predetermined area and in accordance with a procedure comprising the steps of:
Dependencies are inferred from the claim text.