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US 4,908,751 AGranted
Parallel data processor
AssigneeNone recorded
InventorHarry F. Smith
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AssigneeNone recorded
InventorHarry F. Smith
Estimating the term…
A data processing system for simultaneously processing a plurality of data words, comprising one or more data processing planes each of which comprises a plurality of processing entities logically organized as rows and columns as a two dimensional array of processing entities, each of the processing entities being operable for performing arithmetic and logical operations on data words in a substantially simultaneous manner with others of the processing entities. Substantially all of the processing entities are operatively coupled to at least one other processing entity in an immediately adjacent row or column for transferring data therebetween and are also further operatively coupled to at least one other processing entity in a nonadjacent row or column for transferring data therebetween.
A data processing system for simultaneously processing a plurality of data words, the data words being provided by means for generating data words coupled to the system for inputting data words to be processed thereto, the system comprising:
A parallel data processing system for simultaneously processing a plurality of data words generated by a plurality of energy sensors, each of said sensors having an output coupled to said system, comprising:
A method of simultaneously processing a plurality of data words with a first two-dimensional array of discreet data processing elements, individual ones of the data words being generated by individual ones of a plurality of energy sensors organized as an array of energy sensors each of which views an environment and is responsive to energy received from the environment to generate at least one data word expressive of a characteristic of the received energy, each of the energy sensors having an output signal coupled to an associated data processing element for outputting generated data words thereto, the method comprising the steps of:
A parallel data processing system, the system having input terminals for coupling to a two-dimensional array comprised of a plurality of energy sensors each of which has an output signal for expressing a characteristic of energy received from an environment, the two-dimensional array of energy sensors being of the type wherein individual energy sensors of the array are disposed in a two-dimensional pattern wherein a given energy sensor is surrounded by physically adjacent and also by physically nonadjacent energy sensors, the system including an array comprised of a plurality of data processing elements each of which comprises input means coupled to at least one of the input terminals for receiving an output signal from at least one of the energy sensors, individual ones of said data processing elements further comprising means for coupling to a plurality n of logically adjacent data processing elements for transferring data therebetween, individual ones of said data processing elements further comprising means for coupling to a plurality m of logically nonadjacent data processing elements for transferring data therebetween, wherein data transferred between any two logically adjacent processing elements corresponds to data expressive of output signals generated by two energy sensors that are physically adjacent to one another within the two-dimensional pattern, and wherein the data transferred between any two logically nonadjacent data processing elements corresponds to data expressive of output signals generated by two energy sensors that are not physically adjacent to one another in the two-dimensional pattern, individual ones of the data processing elements each further comprising means for executing a stored program for processing an output signal received from at least one associated energy sensor to which the data processing element is coupled, the output signal being processed in conjunction with data received from n logically adjacent data processing elements and in conjunction with data received from m logically nonadjacent processing elements.
Dependencies are inferred from the claim text.
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Single instruction multiple data [SIMD] multiprocessors: three-dimensional arrays or hypercubes
Neural networks: interfaces, programming languages or software development kits, e.g. for simulating neural networks
General purpose image data processing: processor architectures; Processor configuration, e.g. pipelining
Computing and data processing
Term ended 15 Oct 2007 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
This application is related to a copending application Ser. No.: 07/031,035, filed Mar. 27, 1987, entitled "Minimal Connectivity Data processing System", the disclosure of which is incorporated herein in its entirety.
This application relate generally to digital data processing systems and, in particular, relates to a highly parallel digital data processing system wherein individual processing entities (PEs) within a two dimensional processing array (PA) of PEs are each coupled to at least one logically adjacent PE and also to at least one logically nonadjacent PE.
Parallel digital data processing systems are advantageously employed for those computing applications wherein a large amount of data must be analyzed in a relatively short interval of time. By allocating a plurality of data processing elements, such as microprocessors, to simultaneously process the data substantial processing speed improvements are achieved over a traditional single instruction stream, single data stream data processor. Applications where such parallel data processing systems are most beneficial include seismic, meteorologic and imaging applications.
The foregoing features of the present invention will be more fully described hereinafter in the Detailed Description of the Invention read in conjunction with the Drawing wherein:
FIG. 1 is a block diagram of an imaging system 1 comprised of a radiation detecting array 2, a processing array 3 and a control CPU 5;
FIG. 2 is a block diagram of one plane 3a of processing array 3 showing the connectivity of the processing entities 4 contained thereon;
Referring now to FIG. 1 there is shown in block diagram form a digital data processing system 1 having an array of energy detectors 2a. Array 2 is disposed for receiving incident energy, indicated by the letter A, from an environment viewed by each of the detectors. The incident energy may be electromagnetic, thermal or acoustic energy. Each of the detectors 2a are selected for converting the particular type of energy received into a signal 2b having a magnitude which is a function of intensity, frequency, or some other characteristic of the energy. The array 2 may comprise a two dimensional array of detectors organized as rows and columns, although other array topologies are within the scope of the teaching of the invention. The total number of detectors 2a may be arbitrarily large, such as an array of 1024 or even greater.
Each of the signals 2b is coupled to at least one plane of a processing array (PA) 3, the array 3 being comprised of one or more logical planes, such as the planes 3a-d. Each of the planes, such as the plane 3a, is comprised of a plurality of processing entities (PEs) 4.
Referring to FIG. 3 there is shown one possible embodiment of one of the plurality of PEs 4 wherein it can be seen that the PE is a single-chip type of microprocessor device having internal program memory (PMEM) 20, random access memory (RAM) 22, instruction decode and control (IDC) logic 24 and an arithmetic/logic unit (ALU) 26 coupled together by a data bus 28. The PE 4 may also comprise a plurality of communications (COM1-COM12) ports 30a-30l for coupling the PE to other adjacent and nonadjacent PEs in the manner depicted in FIG. 2. The PE 4 may also be provided with one or more clock (CLK) inputs, such as a clock for timing the operation of the IDC 24 and a communications clock if the COM ports 30a-30l are synchronous or asynchronous serial data communication devices. The PE 4 may also have an interrupt output (INT) coupled to a control CPU 5 and a control bus (CONTBUS) coupled to the CPU 5, such as a parallel data bus or a serial or a three wire handshaking bus, as