Data processing device with parallel circular addressing hardware

Abstract

A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme. If the calculated memory address is outside of the block limits, an adder/substractor in the auxiliary arithmetic logic units either adds or subtracts the block size to or from the calculated memory address, so that the result is an address at the other end of the block. The result of the calculation, whether or not modified, is stored in a memory address register. The pair of auxiliary arithmetic logic units are operable in parallel with each other, and in parallel with the primary arithmetic logic unit. The two memory addresses are presented to the on-chip memory in time-multiplexed fashion, so that two memory accesses may be performed in a single machine cycle.

Dependencies are inferred from the claim text.