Self packaging chip mount
AssigneeGeneral Electric Company
InventorHarold F. Webster
Life of this patent
Estimating the term…
Abstract
A method of self packaging an integrated circuit chip (10) on a printed circuit board (14) where conductive leads (16) form an electrical connection with interconnect leads (12) on the printed circuit board (14). A centering frame (22) placed on the printed circuit board serves to align the leads (12 and 16). A cooling cap (34) which dissipates heat from the integrated circuit chip (10) is placed over the centering frame (22) and integrated circuit chip (10). In one embodiment, the leads (12 and 16) form a pressure fit and the cooling cap (34) forces the pressure-fit electrical connections. In another embodiment, the leads (12 and 16) make rubbing contact with each other.
Claims2
An integrated circuit chip assembly for use in a self packaging chip mount, comprising:
- an integrated circuit chip, said integrated circuit chip having side surfaces and terminals on a bottom side;
- a compliant backing member disposed about, and in contact with, a periphery of said bottom and side surfaces of said integrated circuit chip;
- and
- conductive leads secured to said terminals and extending over said compliant backing member on both the said bottom side and side surfaces.
Dependencies are inferred from the claim text.