FET with a super lattice channel

An electronic device as in claims 1, 9, or 6 where said first and second impurity regions are the source and drain of an insulated gate field effect transistor and said superlattice structure is the gate region extending between the source and drain.

An electronic device comprising

• a substrate within which first and second impurity regions and a superlattice structure between said first and second impurity regions are formed where the superlattice structure has upper and lower surfaces extending between the first and second impurity regions;
• and
• wherein said first and second impurity regions are respectively curved toward the opposite ends of the superlattice structure so that the length of the superlattice structure between the first and second impurity regions is less at a lower level beneath the upper surface of the superlattice structure than at said upper surface of the superlattice structure in order to define a lower resistance inner channel within the superlattice structure between the first and second impurity regions.

A gate insulated field effect transistor comprising:

• a substrate within which source and drain regions and a gate region between said source and drain regions are formed and where the gate region has an upper surface, the gate region consisting of a superlattice structure;
• wherein the channel length of said gate region between said source and drain regions is less at a lower level beneath the upper surface of the gate region than at said upper surface of the gate region in order to define a low resistance inner channel within the gate region between the source and drain regions.