High voltage power IC process
AssigneeNational Semiconductor Corporation
InventorsChenming Hu, Steven P. Sapp
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Abstract
A process is disclosed for forming an oxide isolated semiconductor wafer which can include the formation of an associated high voltage transistor. The same wafer can include a plurality of low voltage transistors which can be connected in the form of circuitry that can control the high voltage transistor. Thus, a single IC chip can be fabricated for a power control function. The process includes bonding a first wafer to a second wafer using oxide (11/14), forming a groove (18) through the oxide (15), backfilling with epitaxially regrown semiconductor (19) to provide a high voltage section, and subsequently forming the high voltage transistor, e.g. NPN or DMOS devices, in said section.
Claims8
A process for forming high voltage transistors in a semiconductor wafer which will include low voltage conventional transistors, said process including the steps:
- starting with a first wafer of semiconductor material having a resistivity suitable for the fabrication of said low voltage transistors and a second wafer of semiconductor material having a resistivity that is substantially lower than that of said first wafer;
- forming at least one epitaxial layer of semiconductor material on one face of said second wafer;
- polishing a face of said first wafer and the face of said epitaxial layer of said second wafer to produce flat mirror finishes thereon;
- forming an oxide on each wafer on said polished faces;
- washing said oxide coated wafer faces to render them hydrophilic;
- placing said hydrophilic faces together to produce adhesion between said first and second wafers;
- heating said adhered wafers to coalesce said oxide coatings thereby to join said first and second wafers into a unitary structure;
- grinding and etching said exposed face of said first wafer until a predetermined thickness thereof remains;
- etching a groove in said first wafer that extends through it and through said oxide that joins said wafers together to expose a portion of said epitaxial layer;
- backfilling said groove with epitaxially deposited semiconductor material;
- shaping the exposed surface of said first wafer for subsequent planar processing;
- and
- forming a high voltage transistor in said backfilled semiconductor material.
Dependencies are inferred from the claim text.