US 4,908,327 AGranted

Counter-doped transistor

AssigneeTexas Instruments Incorporated

InventorRichard A. Chapman

Life of this patent

Estimating the term…

Loading patent…

Abstract

P channel and N channel CMOS FETs (22, 24) and a process for their simultaneous fabrication with a minimal number of masking steps are disclosed. After formation of gates (30, 32) for both P channel FETs (24) and N channel FETs (22), a first N type dopant implanting step forms lightly doped drain extensions in both the P channel FETs (24) and the N channel FETs (22). A mask then protects the N channel FET area (22) while a P type dopant is implanted in source and drain regions (36) of the P channel FET (24) at a greater concentration than the prior implanted N type dopant. Another N type dopant implant occurs to both the P channel FET (24) and N channel FET (22). The N type dopant dosage used in this second N type dopant implantation step is greater than the dosage used in the first N type dopant implantation step. Another mask is used to protect the N channel FET (22) while a second P type dopant is implanted into source and drain regions of the P channel FET (24) at a greater concentration than is used in any of the previous implantation steps. Due to the high diffusion rate of the P type dopant, an annealing step drives the P type dopant so that the P channel FET (24) source and drain regions (36) reach the active transistor region underneath the gate.

Claims19

Dependent claims

A method for forming a field effect transistor having lightly doped regions, comprising the steps of:

providing a substrate;
forming a patterned layer on said substrate;
performing a first implantation of first dopant atoms into said substrate, said first dopant atoms having a characteristic of forming regions of a first conductivity type when implanted into said substrate, said patterned layer serving as a mask to prevent implantation of said first dopant atoms in said substrate;
forming first spacer layers on at least one sidewall of said patterned layer;
performing a second implantation of second dopant atoms into said substrate, said second dopant atoms having a characteristic of forming regions of a second conductivity type when implanted into said substrate, said patterned layer and said spacer layers serving as a mask to prevent implantation of said second dopant atoms, said second dopant atoms having a higher rate of diffusion in said substrate than said first dopant atoms;
forming a second spacer layers on said first spacer layers;
performing a third implantation of third dopant atoms into said substrate, said third dopant atoms having a characteristic of forming regions of a first conductivity type when implanted into said substrate, said patterned layer, said first spacer layers and said second spacer layers serving as a mask to prevent implantation of said third dopant atoms in said substrate;
forming third spacer layers on said second spacer layers;
performing a fourth implantation of fourth dopant atoms into said substrate, said fourth dopant atoms having a characteristic of forming regions of a second conductivity type when implanted into said substrate, said patterned layer and said first second and third spacer layers serving as a mask to prevent implantation of said fourth dopant atoms, said fourth dopant atoms having a higher rate of diffusion in said substrate than said third dopant atoms;
heating said substrate to diffuse said first, second, third and fourth dopant atoms into said substrate.

7 more elements

A method for forming a field effect transistor having lightly doped regions, comprising the steps of:

providing a substrate having a first device area and a second device area;
forming a patterned layer on said substrate;
performing a first implantation of first dopant atoms into said substrate, said first dopant atoms having a characteristic of forming regions of a first conductivity type when implanted into said substrate, said patterned layer serving as a mask to prevent implantation of said first dopant atoms in said substrate;
forming first spacer layers on at least one sidewall of said patterned layer;
forming and patterning a first masking layer on said substrate, said first masking layer protecting said second device area;
performing a second implantation of second dopant atoms into said substrate, said second dopant atoms having a characteristic of forming regions of a second conductivity type when implanted into said substrate, said patterned layer, said first masking layer and said spacer layers serving as a mask to prevent implantation of said second dopant atoms, said second dopant atoms having a higher rate of diffusion in said substrate than said first dopant atoms;
forming second spacer layers on said first spacer layers;
performing a third implantation of third dopant atoms into said substrate, said third dopant atoms having a characteristic of forming regions of said first conductivity type when implanted into said substrate, said patterned layer, said first spacer layers and said second spacer layers serving as a mask to prevent implantation of said third dopant atoms in said substrate;
forming third spacer layers on said second spacer layers;
forming and patterning a second masking layer on said substrate, said second masking layer protecting said second device area;
performing a fourth implantation of fourth dopant atoms into said substrate, said fourth dopant atoms having a characteristic of forming regions of said second conductivity type when implanted into said substrate, said patterned layer, said second masking layer and said first, second and third spacer layers serving as a mask to prevent implantation of said fourth dopant atoms, said fourth dopant atoms having a higher rate of diffusion in said substrate than said third dopant atoms;
heating said substrate to diffusion said first, second, third and fourth dopant atoms into said substrate.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/189,262Filed 2 May 1988
Granted: 13 Mar 1990
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 62/151
Source or drain regions of field-effect devices: of igfets
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions