Process for fabricating self-aligned silicide lightly doped drain MOS devices

A method for fabricating an MOS structure, said method comprising the steps of:

• providing a silicon substrate;
• prior to the definition of source and drain regions in said substrate, defining a polysilicon gate on said substrate;
• depositing a first layer of a first material over said polysilicon gate and over at least a portion of the upper surface of said substrate, said first material having a different etch characteristic than said silicon substrate;
• depositing a second layer of a second material having a different etch characteristic than said first material;
• using said first layer of said first material as an etch stop, subjecting the structure to an etch to form a side wall spacer about said polysilicon gate;
• subjecting the structure to a different etch to remove said first layer not covered by said second layer and then selectively depositing or growing additional material to a thickness less than that of said first layer, thereby to form a third layer having a thickness less than that of said first layer;
• thereafter removing said second layer;
• and
• thereafter forming source and drain regions in the upper surface of said substrate by sequentially performing a light and a heavy ion implant of an impurity of the same polarity through said remaining first and third layers.