Satellite delay simulation system

Abstract

Equipment for testing a digital satellite communication system in which multiple digital satellite communication terminals are interconnectable over multiple channels. The equipment includes a single satellite delay simulator intervening between transmit communication terminals and receive communication terminals. The delay simulator is implemented by a satellite delay circuit accommodating multiple channels, and clock matching circuits each being connected to the output or the input of the delay circuit, whereby the communication terminals are individually connectable to the delay circuit via the clock matching circuits. With this configuration, the equipment tests the system by applying a satellite delay simulation to all of the communication terminals, which are operating on independent clocks, at the same time and by using a single satellite delay simulator.

Dependencies are inferred from the claim text.