Dual-rail processor with error checking at single rail interfaces

A dual processor computer system with interprocessor error checking capability comprising:

• a first central processing unit executing a series of instructions including output instructions containing data to be written;
• a second central processing unit executing said series of instructions independently of and in synchronism with said first central processing unit;
• a first data bus coupled to said first central processing unit for receiving said data contained in said output instructions executed by said first central processing unit;
• a second data bus coupled to said second central processing unit for receiving said data contained in said output instructions executed by said second central processing unit;
• a main memory unit into which said data contained in selected ones of said output instructions is to be written;
• memory controller means, coupled between said main memory unit and said first and second data busses, for receiving said data from said first and second data busses substantially simultaneously, for controlling transfer of said data from said first and second data busses to said main memory unit and for checking said data for errors prior to the transfer of said data to said main memory unit, said memory controller means including
• a primary memory controller coupled to said first data bus and including means for transferring data from said first data bus to said main memory unit, and
• a mirror memory controller coupled to said first and second busses and including means for comparing the data from said second data bus with the data from said first data bus for purposes of error checking;
• and
• error checking means, coupled to said first and second data busses, for checking said data received by said memory controller and correcting any errors in said data only when selected ones of said output instructions are executed to write data into said main memory.

A fault tolerant computing system comprising:

• a first dual processor computer system including
• a first central processing unit executing a series of instructions including output instructions containing data to be written into a first designated system element,
• a second central processing unit executing said series of instructions independently of and in synchronism with said first central processing unit,
• a first data bus coupled to said first central processing unit for receiving said data from said first central processing unit.
• a second data bus coupled to said second central processing unit for receiving said data from said second central processing unit,
• first shared resource means, coupled to said first and second data busses, for service as a first designated system element for selected ones of said output instructions executed by said first and second central processing units, for simultaneously receiving said data from said first and second central processing units, and for recording the data contained in said ones of said selected output instructions, said first shared resource means including
• a first memory for storing said data,
• first data selection means for transmitting data from only one of said first and second processing units to said first memory, and
• first error checking means, coupled to said first and second data busses, for checking said data on said first and second data busses to detect and correct errors only following execution of an output instruction, said detection and correction occurring prior to transmission of said data from said first and second central processing unit to said first memory;
• a second dual processor computer system including
• a third central processing unit executing said series of instructions including output instructions containing data to be written into a second designated system.
• a fourth central processing unit executing said series of instructions independently of and in synchronism with said third central processing unit,
• a third data bus coupled to said third central processing unit for receiving said data from said third central processing unit,
• a fourth data bus coupled to said fourth central processing unit for receiving said data from said fourth central processing unit,
• second shared resource means, coupled to said third and fourth data busses, for serving as a second designated system element for selected ones of said output instructions executed by said third and fourth central processing units, for simultaneously receiving said data from third and fourth central processing units, and for recording said data contained in said selected output instructions, said second shared resource means including
• a second memory for storing said data,
• second data selection means for transmitting data from only one of said third and fourth central processing units to said second memory, and
• second error checking means, coupled to said third and fourth data busses, for checking said data on said third and fourth data busses to detect and correct errors only during execution of an output instruction, said detection and correction occurring prior to transmission of said data from said first and second central processing units to said second memory;
• and
• cross-link communication means coupled between said first and second dual processor computer systems for providing bidirectional communication between said first and second dual processor computer systems and for synchronizing said first and second dual processor computer systems.

A dual processor computer system with error checking capability comprising:

• a first processing system for executing a series of instructions including output instructions containing data to be written into a designated system element;
• a second processing system for executing said series of instructions independently of and in synchronism with said first processing system;
• shared resource means, coupled to said first and second processing systems, for serving as a designated element for to selected ones of said output instructions executed by said first and second processing systems and for writing the data contained in said selected ones of said output instructions, said shared resource means receiving said data from said first and second processing systems substantially simultaneously;
• self-checking means coupled to the shared resource means for enabling the shared resource means to check data written into and read out of said shared resource means to keep track of the number of correctible errors for supervisory purposes;
• and
• error checking means coupled to said shared resource means and to said first and second processing systems for checking and correcting errors in the data received from said first and second processing systems only for an output instruction executed by said first and second processing systems to write data into said shared resource means.