US 4,907,225 AGranted

Data protocol controller

AssigneeAdvanced Micro Devices, Inc.

InventorsDale E. Gulick, Terry G. Lawell, Charles Crowe

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Abstract

An integrated data protocol controller (IDPC)(10) is disclosed which includes on a single chip a data link controller (DLC)(52), a universal asynchronous receiver-transmitter (UART)(54) and a dual port timing controller (DPTC)(56). The IDPC is designed to support bit-oriented protocols such as is used in integrated services digital networks (ISDN). A microprocessor interface (50) on the IDPC chip permits a user to control and monitor the IDPC functions via a local microprocessor (18). The IDPC can be connected to a host processor (595) which shares a random access memory (RAM)(22a) with the local processor, allowing interprocessor communication via memory-resident buffers and mailboxes. A set of control and status registers is available within each of the main blocks of the IDPC--the DLC, the UART and the DPTC--to permit user access and control of the respective blocks. The DLC, the UART and the DPTC provide enhanced functions beyond those available in individual chips realizing a DLC, a UART or a DPTC.

A bit-oriented protocol (BOP) data controller (10) fabricated as a single integrated circuit having an internal bus (58,60,62), bidirectional serial port means (104) for high-speed serial receipt and transmission of data signals, full-duplex means (42,44) for low-speed serial receipt and transmission of data signals, and a microprocessor interface means (50) connected to said internal bus for the connection of a microprocessor (18), said BOP data controller comprising:

a data link controller (DLC) (52) connected to said internal bus, to said microprocessor interface means and to said serial port means, comprising transmitter means (100,102) for parallel reception of data on said internal bus, for parallel-to-serial conversion thereof, and for serial generation thereof at said serial port means, and receive means (106,108) for serial reception of data on said serial port means for serial-to-parallel conversion thereof and for parallel generation thereof on said internal bus;
a universal asynchronous receiver-transmitter (UART) (54) connected to said microprocessor interface means, to said internal bus, and to said full-duplex means, comprising transmitter means (418,420,422,424,428) for parallel reception of data on said internal bus, for parallel-to-serial conversion thereof, and for serial generation thereof at said full-duplex means, and receiver means (400,404,410,412) for serial reception of data on said full-duplex means, for serial-to-parallel conversion thereof and for parallel generation thereof on said internal bus;
and
dual-port timing controller (DPTC) means (56) connected to said internal bus, to said microprocessor (18), to a host processor (595) and a shared RAM (22a) and bus arbitration means (502,504,506,508,510,512) for connecting said microprocessor and said host processor to said BOP data controller, for generating timing and control signals to said microprocessor, said host processor, said bus arbitration means and said shared RAM, whereby said shared RAM and said BOP data controller is accessible to both said microprocessor and said host processor.

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Abstract

Claims44