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US 4,907,203 AGranted
Semiconductor memory device with changeable word organization modes including a test mode
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTomohisa Wada, Kenji Anami
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Abstract
A semiconductor memory device comprises a memory cell array, a row decoder, a column decoder, a plurality of sense amplifiers, a plurality of write circuits, a signal switching circuit, a plurality of input buffers, a plurality of output buffers and a plurality of terminals, which are formed on the same chip. A switching signal B1/B4 is applied to one of the plurality of terminals. The semiconductor memory device has a 256K word by 4 bit organization when the switching signal B1/B4 is at an "L" level and has a 1M word by 1 bit organization when the switching signal B1/B4 is at an "H" level. The word organization can be switched mainly by the signal switching circuit.
Claims11
A semiconductor memory device, comprising:
- a semiconductor chip;
- a plurality of terminals formed on said chip for receiving or generating data and address signals,
- said memory device operable selectively in a first word organization mode defined by a first predetermined arrangement of functions of said terminals together with a first word length and in a second word organization mode comprising a test mode defined by a second predetermined arrangement of functions of said terminals together with a second word length different from the first word length;
- means for receiving a word organization mode selection signal;
- and
- signal flow path control circuitry on said chip and responsive to said word organization mode selection signal for operating said chip, selectively, in said first or second word organization mode.
3 more elements
A method of operating a semiconductor memory device, comprising:
- a semiconductor chip;
- a plurality of terminals formed on said chip for receiving or generating data and address signals,
- said memory device operable selectively in a first word organization mode defined by a first predetermined arrangement of functions of said terminals together with a first word length and in a second word organization mode defined by a second predetermined arrangement of functions of said terminals together with a second word length longer than said first word length;
- means for receiving a word organization mode selection signal;
- and
- signal flow path control circuitry on said chip and responsive to said word organization mode selection signal for operating said chip, selectively, in said first or second word organization mode,
- wherein said semiconductor memory device is operable in normal and testing modes of operation;
- said operating method comprising the steps of:
- during said normal mode of operation of said semiconductor device, generating a first word organization mode selection signal corresponding to said first word length;
- during said testing mode of operation of said semiconductor device, generating a second word organization mode selection signal corresponding to said second word length;
- and
- applying said first or second word organization mode selection signal so generated to said word organization mode selection signal receiving means.
9 more elements
A semiconductor memory device comprising:
- a semiconductor chip,
- a plurality of memory cells formed on said semiconductor chip,
- a plurality of terminals formed on said semiconductor chip and receiving data and address signals,
- first processing means formed on said semiconductor chip and having the first number of address input portions receiving the address signals through some of said plurality of terminals and the second number of data receiving portions receiving the data, and responsive to the address signals applied to said address input portions for selecting said second number of memory cells, of said plurality of memory cells and writing the data applied to said data receiving portions to the selected memory cells or reading out the data stored in the selected memory cells o said data receiving portions,
- second processing means formed on said semiconductor chip and having the third number of address input portions receiving the address signals through some of said plurality of terminals and the fourth number of data receiving portions receiving the data, and responsive to the address signals applied to said address input portions for selecting said fourth number of memory cells, of said plurality of memory cells and writing the data applied to said data receiving portions to the selected memory cells or reading out the data stored in the selected memory cells to said data receiving portions,
- switching signal generating means formed on said semiconductor chip for generating a switching signal, and
- signal switching means formed on said semiconductor chip and responsive to a first state of said switching signal generated by said switching signal generating means for coupling said address input portions and said data receiving portions in said first processing means to predetermined terminals, of said plurality of terminals, and responsive to a second state of said switching signal generated by said switching signal generating means for coupling said address input portions and said data receiving portions in said second processing means to a predetermined terminal, of said plurality of terminals.
4 more elements
Dependencies are inferred from the claim text.