US 4,907,201 AGranted

MOS transistor circuit

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsHiroshi Minami, Koreaki Fujita

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Abstract

In a MOS transistor circuit (comprising a pair of current mirror circuits, each comprising: first and second MOS transistors having their gate electrodes connected together third and fourth MOS transistors respectively connected in series with the first and second transistors, the third and the fourth MOS transistors of the pair of current mirror circuits receiving a pair of complementary signals at their gate electrodes; and the nodes between the second and the fourth MOS transistors forming output nodes of the current mirror circuit), a pair of capacitors each coupling the output of one current mirror circuit to the gate electrodes of the first and the second MOS transistors of the other current mirror circuit. This provides positive feedback. The change in the outputs responsive to change in the inputs is thereby accelerated.

Claims5

Dependent claims

A semiconductor memory device, comprising:

a plurality of memory cells, each of which delivers a complementary pair of bitline signals when accessed;
and at least one sense amplifier connected to receive said bitline signals from an accessed one of said cells;
wherein said sense amplifier comprises first and second voltage amplifiers, each including:
first and second active loads;
first and second drive transistors, connected to pull current through said first and second active loads respectively;
said first drive transistor and active load being connected at a first node, which is also connected to regulate the impedance of said first and second active loads, and said second drive transistor and active load being connected at a second node, which is also connected to provide an output signal of said voltage amplifier;
said first drive transistor of said first voltage amplifier and said second drive transistor of said second voltage amplifier being connected to receive one of said bitline signals, and said first drive transistor of said second voltage amplifier and said second drive transistor of said first voltage amplifier being connected to receive the other one of said bitline signals;
said second node of said first voltage amplifier also being coupled to partially drive said first node of said second voltage amplifier, and said second node of said second voltage amplifier also being coupled to partially drive said first node of said first voltage amplifier.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/218,888Filed 14 Jul 1988 · continuation
Priority: JP 61-1042927 May 1986
Granted: 6 Mar 1990
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H03K 3/3565
Bistable circuits: bistables with hysteresis, e.g. Schmitt trigger
H03F 3/45076
With semiconductor devices only: characterised by the way of implementation of the active amplifying circuit in the differential amplifier
H03F 3/45179
Characterised by the way of implementation of the active amplifying circuit in the differential amplifier: using MOSFET transistors as the active…
H03F 2203/45364
Indexing scheme relating to differential amplifiers: the AAC comprising multiple transistors parallel coupled at their gates and sources only,…