US 4,907,200 AGranted

Dynamic memory

AssigneeKabushiki Kaisha Toshiba

InventorsTatsuo Ikawa, Katsushi Nagaba

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Abstract

A dynamic memory having pairs of bit lines. A sense amplifier is connected between each pair of bit lines for detecting data from the potential difference between these bit lines. The memory further comprises first and second pair of dummy word lines. A capacitor is coupled between the first of each pair of bit lines, on the one hand, and the first pair of dummy word lines, on the other. Similarly, a capacitor is coupled between the second of each pair of bit lines, on the one hand, and the second pair of dummy word lines, on the other. A first dummy word line driver is connected to the first pair of dummy word lines, for generating a reference potential in the first of each pair of bit lines. A second dummy word line driver is connected to the second pair of dummy word lines, for generating a reference potential in the second of each pair of bit lines. The memory also has a selection circuit for selecting either the first or second dummy word line driver. During a precharging period, either dummy word line driver sets both pairs of dummy word lines at a precharging potential. During a data-reading period, the dummy word line driver selected by the selection circuit sets the dummy word lines at a high potential and a low potential, respectively, and the dummy word line driver selected by the selection circuit sets both dummy word lines at a precharging potential.

Claims17

Dependent claims

A dynamic memory comprising:

pairs of bit lines;
a plurality of memory cells connected to each pair of bit lines;
a plurality of word lines for selecting the memory cells;
a precharging potential source for precharging said pairs of bit lines during a precharging period which precedes a data-reading period;
a high-potential source;
and
a low-potential source;
a plurality of sense amplifiers, each connected between a pair of bit lines, for detecting data during the data-reading period from a potential difference between the pair of bit lines;
a first pair of dummy word lines;
a second pair of dummy word lines;
first capacitors, each connected between said first pair of dummy word lines, on the one hand, and the first of the corresponding pair of bit lines, on the other hand, for generating a reference potential;
second capacitors, each connected between said second pair of dummy word lines, on the one hand, and the second of the corresponding pair of bit lines, on the other hand, for generating a reference potential;
a first dummy word line driving circuit connected to said first pair of dummy word lines, for generating the reference potential in the first of each pair of bit lines;
a second dummy word line driving circuit connected to said second pair of dummy word lines, for generating the reference potential in the second of each pair of bit lines;
and
a selection circuit for selecting either said first dummy word line driving circuit or said second dummy word line driving circuit,
wherein during said precharging period, said first and second dummy word line driving circuits set said first and second pairs of dummy word lines at the potential of said precharging potential source, and during said data-reading period, the dummy word line driving circuit selected by said selection circuit sets the pair of dummy word lines at the potential of said high-potential source and the potential of said low-potential source, respectively, and the dummy word line driving circuit not selected by said selection circuit sets the pair of dummy word lines at the potential of said precharging potential source.

14 more elements

A dynamic memory comprising:

pairs of bit lines;
a plurality of memory cells connected to each pair of bit lines;
a plurality of word lines for selecting the memory cells;
a precharging potential source for precharging said pairs of bit lines during a precharging period which precedes a data-reading period;
a high-potential source;
and
a low-potential source;
a plurality of sense amplifiers, each connected between a pair of bit lines, for detecting data during the data-reading period from a potential difference between the pair of bit lines;
a first pair of dummy word lines;
a second pair of dummy word lines;
first capacitors, each connected between said first pair of dummy word lines, on the one hand, and the first of the corresponding pair of bit lines, on the other hand, for generating a reference potential;
second capacitors, each connected between said second pair of dummy word lines, on the one hand, and the second of the corresponding pair of bit lines, on the other hand, for generating a reference potential;
a first dummy word line driving circuit connected to said first pair of dummy word lines, for generating the reference potential in the first of each pair of bit lines;
a second dummy word line driving circuit connected to said second pair of dummy word lines, for generating the reference potential in the second of each pair of bit lines;
and
a selection circuit for selecting either said first dummy word line driving circuit or said second dummy word line driving circuit,
wherein each of said dummy word line driving circuits comprises:
first MOS transistor connected between the first of the pair of dummy word lines and said precharging potential source;
second MOS transistor connected between the second of the pair of dummy word lines and said precharging potential source;
third MOS transistor connected between the first of the pair of dummy word lines and said high-potential source, said third MOS transistor being turned on during said data-reading period when selected by said selection circuit;
fourth MOS transistor connected between the second of said pair of dummy word lines and said low-potential source, said fourth MOS transistor being turned on during said data-reading period when selected by said selection circuit;
and
a gate circuit connected to receive a precharge control signal and an output signal of said selection circuit, for turning on said first and second MOS transistors during said precharging period, and for turning on said third and fourth MOS transistors during said data-reading period when said selection circuit outputs no signals.

20 more elements

A dynamic memory comprising:

a plurality of pairs of bit lines;
a plurality of memory cells connected to each pair of bit lines;
a plurality of word lines for selecting the memory cells;
a plurality of potential source for precharging said pairs of bit lines during a precharging period which precedes a data-reading period;
a high-potential source;
a low-potential source;
a plurality of sense amplifiers, each connected between a pair of bit lines, for detecting data during the data-reading period from a potential difference between the pair of bit lines;
a first pair of dummy word lines;
a second pair of dummy word lines;
first capacitors, each connected between said first pair of dummy word lines and the first pair of the corresponding pair of bit lines, for generating a reference potential;
second capacitors, each connected between said first second pair of dummy word lines and the second of the corresponding pair of bit lines, for generating a reference potential;
a first dummy word line driving circuit connected to said first pair of dummy word lines for generating the reference potential in the first of each pair of bit lines;
a second dummy word line driving circuit connected to said second pair of dummy word lines, for generating the reference potential in the second of each pair of bit lines;
and
a selection circuit for selecting either said first dummy word line driving circuit or said second dummy word line driving circuit,
wherein each of said dummy word line driving circuits comprises:
a first MOS transistor connected between the first of the pair of dummy word lines and said precharging potential source, said first MOS transistor being controlled by a precharge control signal;
a second MOS transistor connected between the second of the pair of dummy word lines and said precharging potential source, said second MOS transistor being controlled by a precharge control signal;
a third MOS transistor connected between the pair of dummy word lines, said third MOS transistor being controlled by the precharge control signal;
a fourth MOS transistor Connected between the first of the pair of dummy word lines and said high-potential source, said fourth MOS transistor being controlled by an output of said selection circuit;
a fifth MOS transistor connected between the second of said pair of dummy word lines and said low-potential source, said fifth MOS transistor being controlled by an output of said selection circuit;
a sixth MOS transistor connected between the first of said pair of dummy word lines and said precharging potential source, said sixth MOS transistor being controlled by an output of said selection circuit;
and
a seventh MOS transistor connected between the second of said pair of dummy word lines and said precharging potential source, said seventh MOS transistor being controlled by an output of said selection circuit.

21 more elements

Dependencies are inferred from the claim text.