US 4,907,199 AGranted

Dynamic semiconductor memory device and method for controllig the precharge/refresh and access modes thereof

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsKatsumi Dosaka, Masaki Kumanoya, Yasuhiro Konishi, Hiroyuki Yamasaki, Takahiro Komatsu

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Abstract

A dynamic semiconductor memory device is divided into a plurality of blocks. An operation of the semiconductor memory device is in either of a normal mode and a refresh mode, depending on the level of a refresh signal. In the normal mode, at an off time period, a potential on a bit line pair is equalized and a precharge potential is applied to the bit line pair. At the access time, equalizing of the potential on the bit line pair and supply of the precharge potential are stopped in a selected block and then, a word line driving signal is raised. On the other hand, in the refresh mode, at the off time period, the potential on the bit line pair is held at "H" and "L" levels by a sense amplifier, so that the potential on the bit line pair is not equalized and the precharge potential is not supplied. On this occasion, a precharge potential generating circuit is electrically disconnected from a power supply. At the time of refresh operation, the sense amplifier is rendered inactive in the selected block, so that the potential on the bit line pair is equalized and then, the word line driving signal is raised.

Claims12

Dependent claims

A dynamic semiconductor memory device, comprising:

a memory cell array divided into a plurality of blocks,
each of said blocks comprising
a plurality of memory cells arranged in a plurality of rows and columns,
a plurality of word lines each provided corresponding to each row of said plurality of memory cells and used for selecting the memory cells in the row,
a plurality of bit line pairs each provided corresponding to each column of said plurality of memory cells and used for writing information to the memory cells in each column or reading out information stored in the memory cells in the column,
a plurality of sense amplifiers each connected to each of said bit line pairs for amplifying a potential on the bit line pair to a first potential and a second potential, respectively, and
a plurality of equalizing means each connected to each of said bit line pairs for equalizing a potential on the bit line pair,
block selecting means for selecting any of said plurality of blocks;
intermediate potential generating means for generating an intermediate potential between said first potential and said second potential and applying the same to each of said bit line pairs;
mode defining means for providing a first mode control signal defining a normal mode and a second mode control signal defining a refresh mode;
and
control means responsive to said first mode control signal defining a normal mode for
(a) rendering inactive said sense amplifiers included in a block selected by said block selecting means;
and
(b) rendering active said equalizing means and said intermediate potential generating means included in the selected block after an access operation in the block is completed;
said control means further responsive to said second mode control signal defining a refresh mode for, prior to starting of the refresh mode
(a) holding active said sense amplifiers included in a block selected by said block selecting means and rendering inactive said equalizing means and said intermediate potential generating means included in the selected block after a refresh operation in the block is completed;
and
(b) rendering inactive said sense amplifiers included in the block immediately before the next refresh operation is performed in the block, rendering said equalizing means active for a predetermined short period of time.

16 more elements

An operating method for a dynamic semiconductor memory device, which includes:

a memory cell array divided into a plurality of blocks,
each of said blocks comprising
a plurality of memory cells arranged in a plurality of rows and columns,
a plurality of word lines each provided corresponding to each row of said plurality of memory cells and used for selecting the memory cells in the row,
a plurality of bit line pairs each provided corresponding to each column of said plurality of memory cells and used for writing information to the memory cells in each column or reading out information stored in the memory cells in the column,
a plurality of sense amplifiers each connected to each of said bit line pairs for amplifying a potential on the bit line pair to a first potential and a second potential, respectively, and
a plurality of equalizing means each connected to each of said bit line pairs for equalizing a potential on the bit line pair,
block selecting means for selecting any of said plurality of blocks;
intermediate potential generating means for generating an intermediate potential between said first potential and said second potential and applying the same to each of said bit line pairs;
said operating method comprising the steps of:
generating a first mode control signal defining a normal mode and a second mode control signal defining a refresh mode;
in response to said first control signal defining a normal mode
(a) rendering inactive said sense amplifiers included in a block selected by said block selecting means;
and
(b) rendering active said equalizing means and said intermediate potential generating means included in the selected block after an access operation in the block is completed;
and
in response to said second mode control signal defining a refresh mode, prior to starting of the refresh mode
(a) holding active said sense amplifiers included in a block selected by said block selecting means and rendering inactive said equalizing means and said intermediate potential generating means included in the selected block after a refresh operation in the block is completed;
and
(b) rendering inactive said sense amplifiers included in the block immediately before the next refresh operation is performed in the block, rendering said equalizing means active for a predetermined short period of time.

17 more elements

Dependencies are inferred from the claim text.