Semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHideaki Arima
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Abstract
An EEPROM formed of three-layer polysilicon is provided. A floating gate is at a second level and a portion thereof is at a first level. A first control gate and a select gate are formed spaced apart from each other at the first level and a portion of the second floating gate extends between them for formation of a tunnel region. A second control gate which is kept at the same potential as the first control gate exist at a third level. In this EEPROM, electrons are drawn from the floating gate by applying a high voltage to the select gate.
Claims9
A semiconductor memory device comprising:
- a semiconductor substrate of a first conductivity type having a main surface and a predetermined impurity concentration;
- a first, second and third impurity regions of a second conductivity type formed spaced apart from each other on the main surface of said semiconductor substrate,
- the area between said first and second impurity regions of the second conductivity type defining a first channel region and the area between said second and third impurity regions of the second conductivity type defining a second channel region;
- a first conductor layer formed on said first channel region through an insulating film;
- a second conductor layer formed on one portion of said second channel region through an insulating film;
- a third conductor layer formed through an insulating film on said second conductor layer, a first region on said second channel region excluding a region on which said second conductor layer is formed, and said second impurity region of the second conductivity type for storing charge representing information in accordance with a voltage applied to said second conductor layer, said second conductor layer having a stepped portion at said first region;
- and
- a fourth conductor layer formed on said third conductor layer through an insulating film,
- the insulating film formed between said third conductor layer, and said second impurity region of the second conductivity type being a thin insulating film for passing a tunnel current and said second conductor layer being electrically connected to said fourth conductor layer.
A semiconductor memory device comprising a semiconductor substrate of a first conductivity type having a main surface and a predetermined impurity concentration and a plurality of memory cells spaced apart and insulated from each other on said semiconductor substrate, said each memory cell comprising:
- a first, second and third impurity regions of a second conductivity type formed spaced apart from each other on the main surface of said semiconductor substrate,
- the area between said first and second impurity regions of the second conductivity type defining a first channel region and the area between said second and third impurity regions of the second conductivity type defining a second channel region;
- a first conductor layer formed on said first channel region through an insulating film;
- a second conductor layer formed on one portion of said second channel region through an insulating film;
- a third conductor layer formed through an insulating film on said second conductor layer, a region on said second channel region excluding a region on which said second conductor layer is formed, and said second impurity region of the second conductivity type for storing charge representing information in accordance with a voltage applied to said second conductor layer, said second conductor layer having a stepped portion at said first region;
- and
- a fourth conductor layer formed on said third conductor layer through an insulating film,
- the insulating film formed between said third conductor layer, and said second impurity region of the second conductivity type being a thin insulating film for passing a tunnel current and said second conductor layer being electrically connected to said fourth conductor layer
- said plurality of memory cells sharing said second conductor layer and said fourth conductor layer, and
- said second conductor layer and said fourth conductor layer being connected at common connection portion to said plurality of memory cells.
Dependencies are inferred from the claim text.