Back to results
US 4,907,196 AGranted
Semiconductor memory device using resonant-tunneling transistor
AssigneeFujitsu Limited
InventorsToshihiko Mori, Toshiro Futatsugi
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device comprises a transistor having such a current characteristic that a base current has a differential negative resistance characteristic and a collector current greatly flows after the differential negative resistance characteristic occurs in the base current when a base-emitter voltage is increased, a load coupled in series between a collector and a base of the transistor, first and second input terminals coupled to the base of the transistor through a base resistance of the transistor, and an ouptut terminal coupled to the collector of the transistor.
Claims26
A semiconductor memory device comprising:
- a transistor having a current characteristic that a base current has a differential negative resistance characteristic and a large collector current flows after the differential negative resistance characteristic occurs in a base current when a base-emitter voltage is increased;
- a load coupled in series to a circuit of a collector and an emitter of said transistor;
- first and second input terminals coupled to the base of said transistor through a base resistance of said transistor;
- and
- an output terminal coupled to the collector of said transistor.
2 more elements
A semiconductor memory device comprising:
- a transistor having such a current characteristic that a base current has a differential negative resistance characteristic and a large collector current flows after the differential negative resistance characteristic occurs in the base current when a base-emitter voltage is increased;
- a load coupled in series to a circuit of a collector and an emitter of said transistor;
- first and second input terminals coupled to the base of said transistor through a base resistance of said transistor;
- and
- an output terminal coupled to the collector of said transistor,
- a write-in operation of said semiconductor memory device being carried out by supplying one of high and low level signals to both said first and second input terminals, a read-out operation of said semiconductor memory device being carried out by supplying a medium level signal to one of said first and second input terminals and a timing pulse signal to the other of said first and second input terminals, said medium level signal having an intermediate level between said high and low levels.
3 more elements
A semiconductor memory device comprising:
- a bit line;
- a word line;
- a read line;
- and
- a memory cell comprising a transistor having such a current characteristic that a base current has a differential negative resistance characteristic and a large collector current flows after the differential negative resistance characteristic occurs in the base current when a base-emitter voltage is increased, a load coupled in series to a circuit of a collector and an emitter of said transistor, first and second input terminals coupled to the base of said transistor through a base resistance of said transistor, and an output terminal coupled to the collector of said transistor,
- said first input terminal being coupled to said first word line,
- said second input terminal being coupled to said bit line,
- said output terminal being coupled to said read line.
5 more elements
A semiconductor memory device comprising:
- a plurality of bit lines;
- a plurality of word lines;
- a plurality of read lines;
- and
- a memory cell array constituted by a plurality of identical memory cells, each of said memory cells being connected to one of said bit lines, one of said word lines and one of said read lines,
- each of said memory cells comprising a transistor having such a current characteristic that a base current has a differential negative resistance characteristic and a large collector current flows after the differential negative resistance characteristic occurs in the base current when a base-emitter voltage is increased, a load coupled in series to a circuit of a collector and an emitter of said transistor, first and second input terminals coupled to the base of said transistor through a base resistance of said transistor, and an output terminal coupled to the collector of said transistor,
- said first input terminal being coupled to a corresponding one of said word lines,
- said second input terminal being coupled to a corresponding one of said bit lines,
- said output terminal being coupled to a corresponding one of said read lines.
6 more elements
Dependencies are inferred from the claim text.