Computer control system and method for effecting sequence controls and servo-controls
AssigneeToshiba Kikai Kabushiki Kaisha
InventorsYoshinari Sasaki, Etsuji Oda, Naoki Kurita, Toshihiko Kaneko
Life of this patent
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Abstract
In a computer system suitable for effecting a sequence control and a servo-control, programs are prepared by using three types of parallel processing instructions consisting of an open instruction, a close instruction is issued from a first program for parallelly processing a second program. The close instruction is issued from the first program to terminate the first or second program. The pause instruction is issued from the first program to stop execution of the first program for a definite interval.
Claims16
A computer system for executing three types of parallel processing instructions including an open instruction, a close instruction and a pause instruction, said computer system comprising:
- a central processing unit (CPU);
- a timer comprising a counter renewed by a definite count at predetermined definite intervals and connected to said CPU to be read thereby;
- program memory means for storing programs of a sequence control and a servo-control to be executed by said CPU;
- a program counter connected to said CPU and said program memory means for designating an address of said program memory means, at which address an instruction to be executed next is stored, and a content of said program counter being renewed according to a type of instruction executed by said CPU;
- an address table connected to said CPU and said program counter for registering addresses of programs designated by an open instruction and a pause instruction, registered addresses of said address table being searched and erased in accordance with a close instruction;
- a time table connected to said CPU and written with a predetermined time from said timer for starting an execution of a program registered in said address table;
- and
- a pointer connected between said address table and said time table and to said CPU for scanning corresponding portions of said address table and said time table.
A computer system for effecting a sequence control and a servo-control, comprising:
- a central processing unit (CPU);
- an interruption clock which applies an interruption signal to said CPU at a predetermined interval;
- program memory means for storing programs of a sequence control and a servo-control to be executed by said CPU;
- a program counter connected to said CPU and said program memory means for designating an address of said program memory means, at which an instruction to be executed next is stored, and a content of said program counter being renewed according to a type of an instruction executed by said CPU;
- a plurality of service circuits connected to said CPU and said program counter, each service circuit including an address table connected to said program counter, a service pointer, a top pointer and a catalogue pointer, said pointers being connected to said address table;
- and
- a pause pointer controlled by said CPU for selecting one of said service circuits having a shortest pause time at an initial state,
- said address table being connected to said program counter for registering addresses of programs designated by an open instruction and a pause instruction, addresses registered in said address table and designated by said service pointer being transferred to said program counter;
- said service pointer designating a position of said address table storing an address of a program now being served;
- said top pointer denoting a leading address of a program to be served and stored in said address table;
- and
- said catalogue pointer denoting a position of said address table written by an open instruction and a pause instruction.
Dependencies are inferred from the claim text.