Cache tag comparator with read mode and compare mode

A cache TAG having an array of bits from which a predetermined number of bits are selected in response to an address for providing a plurality of bit signals representative of corresponding logic states of the selected bits, a read mode for providing, external to the cache TAG, data output signals representative of the logic states of the selected bits, and a compare mode for comparing the logic states of the selected bits to logic states of a plurality of input data signals of the predetermined number, comprising:

• a plurality of comparators of the predetermined number, each comparator for receiving a corresponding bit signal and a corresponding data input signal and for providing, when the cache TAG is in the compare mode, a compare signal at a first logic state if the logic state represented by the received bit signal is the same as the logic state of the corresponding data input signal and at a second logic state if the logic state represented by the received bit signal is not the same as the logic state of the corresponding data input signal and for providing, when the cache TAG is in the read mode, the compare signal at the logic state representative of the corresponding bit signal;
• and
• output means, coupled to the plurality of comparators, for providing, when the cache TAG is in the compare mode, a match signal to indicate if all of the amplified output signals are representative of the compare output signals being in the first logic state and for providing, when the cache TAG is in the read mode, the data output signals at the logic states representative of the selected bits as indicated by the compare signals.

A cache TAG having an array of bits from which a predetermined number of bits are selected in response to an address for providing a plurality of pairs of true and complementary bit signals representative of corresponding logic states of the selected bits and a compare mode for comparing the logic states of the selected bits to logic states of a plurality of input data signals of the predetermined number, comprising:

• a plurality of comparators each corresponding to a particular pair of the pair of true and complementary bit signals and to a particular input data signal of the plurality of input data signals, each comparator comprising:
• a true output;
• a complementary output;
• first coupling means for coupling the true bit signal of the corresponding pair of bit signals to the true output when the corresponding input data signal is in a first logic state;
• second coupling means for coupling the true bit signal to the complementary output when the corresponding input data signal is in a second logic state;
• third coupling means for coupling the complementary bit signal to the complementary output when the corresponding input data signal is in the first logic state;
• and
• fourth coupling means for coupling the complementary bit signal to the true output when the corresponding input data signal is in the second logic state;
• a plurality of secondary sense amplifiers each corresponding to a particular one of the comparators and having a pair of inputs coupled to the true and complementary outputs of the corresponding comparator and an output;
• and
• a match comparator, coupled to the outputs of the plurality of secondary sense amplifiers, which provides a match signal if the outputs of the plurality of secondary sense amplifiers are all in a predetermined logic state.

A cache TAG having an array of bits from which a predetermined number of bits are selected in response to an address for providing a plurality of pairs of true and complementary bit signals representative of corresponding logic states of the selected bits, an and/or/invert mode, and a compare mode for comparing the logic states of the selected bits to logic states of plurality of input data signals of the predetermined number, comprising:

• a plurality of comparators each corresponding to a particular pair of the pair of true and complementary bit signals and to a particular input data signal of the plurality of input data signals, each comparator comprising:
• a true output;
• a complementary output;
• first coupling means for coupling the true bit signal of the corresponding pair of bit signals to the true output when the corresponding input data signal is in a first logic state;
• second coupling means for coupling the true bit signal to the complementary output when both the cache TAG is in the compare mode and the corresponding input data signal is in a second logic state;
• third coupling means for coupling the complementary bit signal to the complementary output when the corresponding input data signal is in the first logic state;
• fourth coupling means for coupling the complementary bit signal to the true output when both the cache TAG is in the compare mode and the corresponding input data signal is in the second logic state;
• first output control means, coupled to the true output, for providing a true control signal at the first logic state to the true output when both the cache TAG is in the and/or/invert mode and the data input signal is in the second logic state;
• and
• second output control means, coupled to the complementary output, for providing a complementary control signal at the second logic state to the complementary output when both the cache TAG is in the and/or/invert mode and the data input signal is in the second logic state;
• a plurality of secondary sense amplifiers each having a pair of inputs coupled to the true and complementary outputs of a corresponding comparator and an output;
• and
• a match comparator, coupled to the outputs of the plurality of secondary sense amplifiers, which provides a match signal if the outputs of the plurality of secondary sense amplifiers are all in a predetermined logic state.