Processing system using cascaded latches in a transmission path for both feedback and forward transfer of data

A data transmission path comprising:

• a self-running type shift register which includes a pre-stage latching means and a post-stage latching means coupled in a cascade fashion and means for pushing-in and popping-up data;
• data processing means coupled between the post-stage latching means and the pre-stage latching means of the self-running type shift register so that said pushing-in and popping-up data means shifts the data from said post-stage latching means to said pre-stage latching means via said data processing means in response to a signal generated by means for detecting vacancy or said pre-stage latching means;
• and
• designating means for decoding a designation code included in the data at the pre-stage latching means and for designating the kind of data processing to be performed in said data processing means, said data processing means being responsive to said designating means for processing the data from said post-stage latching means and said pre-stage latching means in accordance with the kind of the data processing designated by said designating means.

A data processing apparatus, comprising:

• a self-running type shift register including a plurality of latch registers coupled in a cascade fashion, a plurality of coincidence elements for inhibiting transfer of data from a post-stage latch register to a pre-stage latch register when the pre-stage latch register is not vacant and for allowing transfer of data from the post-stage latch register to the pre-stage register when the per-stage latch register is vacant, and means for shifting and latching a predefined data packet into the respective latch registers on a word basis;
• data processing means coupled between the post-stage latch register and the pre-stage latch register for processing operand data from at least one of the post-stage and pre-stage latch registers;
• and
• designating means for decoding an operation code included in a data word at the pre-stage latch register and for designating a kind of data processing t be performed in said data processing means, said data processing means being responsive to said designating means for performing the kind of data processing designated so as to produce a result, said coincident elements allowing the result of data processing in said data processing means to transfer to the pre-stage latch register when the pre-stage latch register is in the vacant state.