Data direct ingest system

An interface device for the synchronous receiving and processing of a first and a second serial data stream of data bits transmitted at high rates from a data source, said data source also transmitting a synchronization signal, said interface device comprising:

• converting means for receiving and converting said serial streams of data bits into data words of parallel bits;
• a First-In-First-Out buffer memory that is loaded with and temporarily stores said data words;
• an output register means connected in parallel to receive the data output from said buffer memory;
• a clock signal producing means responsive to the synchronization signal for producing a plurality of synchronized clocking signals,
• a first clocking signal transmitted to said converting means and used thereby for converting said data bit into data words,
• a second clocking signal transmitted to said buffer memory for clocking out said temporarily stored words asynchronously with respect to the loading of said buffer memory,
• a third clocking signal supplied to said multiplexer means for selecting which received serial data stream is to be transmitted to said buffer memory, and
• a fourth clocking signal supplied to said output register means for latching said buffer memory data output;
• means for detecting when said buffer memory reaches a predetermined state of fullness and for producing a fullness signal indicative of said buffer memory reaching said state;
• and
• means connected to said detecting means and responsive to said fullness signal for enabling the latching of data from said buffer memory by said output register.

A method for receiving and temporarily storing a stream of bits of data broadcasted together with a clock signal and other data by a data source at high rates and for providing the data to a utilization device, the method comprising:

• generating a plurality of timing control signals by using the received clock signal;
• clocking the received data into a shift register with a first generated timing control signal to form a data word;
• clocking out said formed data word in parallel using a second generated timing control signal and temporarily storing said word in a storage register;
• multiplexing said formed data word with other received data using a third generated timing control signal and storing the multiplexed data in a first-in-first-out buffer memory at a first clocking rate;
• detecting the degree of fullness of said buffer memory and generating a flag when said buffer memory reaches a predetermined amount of fullness;
• and
• using said flag to cause a fourth generated timing control signal to be provided to said buffer memory to clock out said stored data on a FIFO basis at a rate greater than said data is clocked into said buffer memory.