Arithmetic operation circuit

An arithmetic operation circuit for a microprocessor comprising:

• a first terminal to which a first power supply voltage is applied;
• a second terminal to which a second power supply voltage smaller than said first power supply voltage is applied;
• input terminals to which input signals to be processed by said arithmetic operation circuit are applied;
• an output terminal;
• logic processing means for performing a predetermined logic operation and including an output node, a first logic circuit having a plurality of first MOSFETS of a first conductivity type, source-drain paths of which are coupled in series between said output node and a selected terminal selected from said first and second terminals, gates of which are coupled to first predetermined input nodes, and a second logic circuit having a plurality of second MOSFETS of said first conductivity type, source-drain paths of which are coupled in series between said output node and said selected terminal, gates of which are coupled to second predetermined input nodes, so that said logic processing means provides an output signal to said output node in accordance with operations of said first and second logic circuit;
• and
• amplifier means coupled to said output node of said logic processing means for amplifying said output signal, and including a bipolar transistor coupled to have its collector-emitter path coupled between said output terminal and said second terminal and its base coupled to receive said output signal of said logic processing means, and a resistor element coupled between said first terminal and said output terminal.

A half adder circuit is an arithmetic operation unit for a one-chip microcomputer comprising:

• a first terminal for supplying a first power supply voltage;
• a second terminal for supplying a second power supply voltage smaller than said first power supply voltage;
• a plurality of input terminals to which input signals (X,X,Y,Y) are applied, respectively;
• first and second output terminals;
• a logic processing circuit including first and second output nodes, first and second MOSFETS having their source-drain paths coupled between said first output node and a selected terminal selected from said first and second terminals and their gates respectively coupled to receive input signals (X,Y), third and fourth MOSFETS having their source-drain paths coupled between said first output node and said selected terminal and their gates respectively coupled to receive said input signals (X,Y) and fifth and sixth MOSFETS having their source-drain paths coupled between said second output node and said selected terminal, and their gates respectively coupled to receive said input signals (X,Y), wherein said first to sixth MOSFETS are all of a first conductivity type;
• a first bipolar transistor coupled to, have a base coupled to said first output node and a collector-emitter path coupled between said first output terminal and said second terminal;
• a first resistor element coupled between said first terminal and said first output terminal;
• a second bipolar transistor coupled to have a base coupled to said second output node and a collector-emitter path coupled between said second output terminal and said second terminal;
• and
• a second resistor element coupled between said first terminal and said second output terminal.

A half subtractor circuit in an arithmetic operation unit for a one-chip microcomputer comprising:

• a first terminal for supplying a first power supply voltage;
• a second terminal for supplying a second power supply voltage smaller than said first power supply voltage;
• a plurality of input terminals to which signals (X,X,Y,Y) are applied, respectively;
• first and second output terminals;
• a logic processing circuit including first and second output nodes, first and second MOSFETS having their source-drain paths coupled between said first output node and a selected terminal selected from said first and second terminals and their gates respectively coupled to receive said signals (X,Y), third and fourth MOSFETS having their source-drain paths coupled between said first output node and said selected terminal and their gates respectively coupled to receive said signals (X,Y) and fifth and sixth MOSFETS having their source-drain paths coupled between said second output node and said selected terminal, and their gates respectively coupled to receive said signals (X,Y), wherein said first to sixth MOSFETS are all of a first conductivity type;
• a first bipolar transistor coupled to have a base coupled to said first output node and a collector-emitter path coupled between said first output terminal and said second terminal;
• a first resistor element coupled between said first terminal and said first output terminal;
• a second bipolar transistor coupled to have a base coupled to said second output node and a collector-emitter path coupled between said second output terminal and said second terminal;
• and
• a second resistor element coupled between said first terminal and said second output terminal.