US 4,907,180 A · Hardware switch level simulator for MOS circuits

Abstract

A hardware switch level simulator for LSI/VLSI MOS circuits capable of simulating circuits with pass transistors and performing timing analysis. The simulator has a stack memory containing lists of nodes to be operated on, a solve unit having programmed logic arrays for performing simulation steps using Bryant algebra plus an addition step for detecting unblocked paths to a controlling gate of a pass transistor, a traversal unit having gate memory storing a gate list of nodes for each transistor and having link memory storing a netlist of transistor switches with parameters such as preset transistor switch state, transistor strength, and pointers to nodes to which a transistor connects. A timing unit performs delay calculations. In order to simulate pass transistor circuits, the traversal unit has two sets of memory addressing gates. One set ordinarily accesses link memory, while a second set ordinarily addresses gate memory. During source to gate path detection, the second set can be multiplexed to also address link memory.

Claims10

Dependent claims

In a computer system for MOS transistor circuit simulation using Bryant algebra for calculating unit delay and performing timing simulation the improvement comprising,

first memory means for storing gate parameters of transistors in a VLSI circuit, including pass transistors, said parameters including identification of transistors whose gates are connected to each node of said circuit,
second memory means for storing path information of said VLSI circuit, including identification of nodes connected to a source and drain of each transistor, a switch state for each transistor and a switch strength for each transistor,
control means communicating with said first and second memory means for retrieving information stored in said first and second memory means, said control means including first gate means for retrieving information in said second memory means and second gate means multiplexed for retrieving information in either one of said first and second memory means,
solve means communicating with the control means for detecting unblocked paths to a controlling gate of each pass transistor.

1 more element

A hardware switch level simulator for MOS transistor circuit simulation comprising,

stack memory means for storing a plurality of sets of nodes to be operated upon,
link memory means for storing information relating to each transistor in an MOS transistor circuit, including pass transistors, said information including identification of nodes connected to a drain and source of each transistor, a switch state of each transistor and a switch strength of each transistor,
gate memory means for storing information relating to each node connected to a transistor gate, said information including identification of transistors whose gates connect to each node,
node memory means for storing information relating to each node in said MOS transistor circuit, said information including pointers to information stored in said link memory means relating to transistors identifying each node and to information stored in said gate memory relating to each node, a node state of each node, an intrinsic node strength of each node and strength information associated with a path to each node,
control means communicating with said stack, link, gate and node memory means for retrieving information stored in said stack, link, gate and node memory means, said control means including a first gate communicating with said link memory means and a second gate mulitplexed to communicate to either one of said gate memory means and link memory means, and
solve means communicating with said stack, link, gate and node memory means via said control means for performing Bryant algebra simulation steps on said sets of nodes, said solve means including means for detecting the condition V.sub.gs <V.sub.th for MOS pass transistors in said circuit, where V.sub.gs is a gate to source voltage for said pass transistor and V.sub.th is a threshold voltage for said pass transistor.

3 more elements

A hardware switch level simulator comprising

a solve unit having a plurality of programmed logic arrays for performing Bryant algebra simulation steps for an MOS transistor circuit including detection of an unblocked path to a controlling gate of a pass transistor, said solve unit also comprising a node memory storing a list of nodes in said circuit with parameters relating to said nodes,
a stack unit communicating with said solve unit and storing stacks of nodes in various sets to be operated on by said programmed logic arrays, and
a traversal unit communicating with said solve unit and having a gate memory storing a gate list of nodes with pointers to transistors whose gates connect to said nodes, said traversal unit also having a link memory storing a netlist of transistors with parameters relating to said transistors and to connections between nodes and transistors, said traversal unit further comprising a first gate means for addressing said gate list stored in said gate memory and a second gate means for addressing said netlist stored in said link memory, said traversal unit also including a state machine communicating with said solve unit and with said first and second gate means to retrieve gate list and netlist information requested by said programmed logic arrays, said state machine multiplexing said first gate means for addressing said netlist of said link memory during said detection of an unblocked gate to a controlling gate of a pass transistor.

Dependencies are inferred from the claim text.

Hardware switch level simulator for MOS circuits

Life of this patent

Hardware switch level simulator for MOS circuits

Life of this patent

Abstract

Claims10