US 4,907,171 A · Image size converter

Abstract

An image size converter includes X1 through X4 value generators for respectively generating X1 through X4 values of an image size, first through fourth adders each of which receives a corresponding one of the X1 through X4 values from the X1 through X4 generators at one input thereof, a register for storing at least a decimal part of the said fourth adder and supplying the decimal part to the other input of each of said first through fourth adders, first through third exclusive ORs for detecting noncoincidence between at least the least significant bits of the integer parts of the sums from the second through fourth adders and of the first through third adders, and a size conversion data generator for receiving an image size conversion object dot pattern input in units of 4 bits and determining correspondence between the 4-bit input dot pattern and the first through 4-bit output dot patterns on the basis of the least significant bit of the integer part of the sum of the first adder, and a detection result of said the first through third exclusive ORs.

Claims51

Dependent claims

An image size converter which receives input dot pattern data, for enlarging or reducing the image size of the input dot pattern data corresponding to a scale value, comprising:

means for inputting the scale value to the image size converter;
means for receiving the scale value and for generating in parallel a plurality of carry signals corresponding to the input scale value;
and
means for receiving in parallel said plurality of carry signals and the input pattern data and for copying the input dot pattern data in accordance with occurrence of a predetermined carry signal, among said plurality of carry signals, when enlarging the image size of the input dot pattern data, and for performing one of thinning and logical ORing the input dot pattern data in accordance with occurrence of the predetermined carry signal, among said plurality of carry signals, when reducing the image size of the input dot pattern data in response to the scale value.

1 more element

An image size converter which receives input dot pattern data for enlarging or reducing an image size in accordance with a scale value to the image size converter;

means, operatively coupled to said inputting means, for receiving said scale value and for generating in parallel a plurality of carry signals;
means for receiving and processing the input dot pattern data and for generating output dot pattern data;
and
means, operatively coupled to receive said carry signals, for controlling the processing of the image pattern data in response to parallel input of said carry signals to modify the output dot pattern data in accordance with the scale value.

1 more element

An image size converter for converting the image size in accordance with a scale value comprising:

first through nth scale generators for generating outputs respectively weighted by factors 1 through n times the scale value, n being an integer of 2 or more;
first through nth adders, each of which receives a corresponding output from said first through nth scale generators at respective first inputs thereof;
a register for holding an output sum from said nth adder and for supplying the output to respective second inputs of each of said first through nth adders;
first through (n-1)th detecting means each connected between an adjacent two adders for detecting noncoincidence between a least significant bit of each sum from respective second through nth adders and of respective first through (n-1)th adders and producing detection results;
and
a size conversion data generator for receiving a dot pattern input in units of n bits and for determining correspondence between the n-bit input dot pattern and a carry signal indicating a carry from a fraction part to an integer part from an addition by said first adder and detection results of said first through (n-1)th detecting means, said size conversion data generator including means for performing a predetermined bit manipulation on the input dot pattern until detecting a predetermined carry signal.

3 more elements

An image size converter which receives input dot pattern data, for enlarging or reducing the image size of the input dot pattern data in accordance with a scale value, comprising:

means for inputting the scale value to the image size converter;
means for receiving the scale value from said inputting means and for generating in parallel a plurality of carry signals;
means for receiving in parallel said plurality of carry signals and the input dot pattern data and for producing output dot pattern data;
said means generating a plurality of carry signals including:
means for generating predetermined multiples of the scale value;
first through nth adding means each of which receives one of said determined multiples of the scale value at a first input thereof, n being an integer of 2 or more;
holding means for holding an output sum from said nth adder and supplying the output sum to a second input of each of said first through nth adders, a content held by said holding means being updated for each of predetermined sets of input dot pattern data;
first through (n-1)th noncoincidence detecting means, each connected between an adjacent two adders, for detecting noncoincidence between a least significant bit of each sum from said second through nth adders and of said first through (n-1)th adders, respectively, and for generating said plurality of carry signals;
and wherein said output sum comprises an integer part and a fraction part, and said first adder outputs another one of said plurality of carry signals having logic "1" representing a carry from a fraction part to an integer part during an addition by said first adder, said first through (n-1)th noncoincidence detecting means upon detecting noncoincidence outputting a carry signal of logic "1", and said means for generating an output dot pattern comprising an image size reduction data generator which comprises:
a reduced data generator which receives n-bit input dot pattern data and receives said plurality of carry signals from said first adder and said first through n-1)th noncoincidence detecting means, and said reduced data generator including means for ORing the input dot pattern data in accordance with occurrence of the carry signal of logic "1" from said first adder or said first through (n-1)th noncoincidence detecting means;
a number-of-carries encoding circuit for receiving the carry signals and generating a carry code representing the number of carry signals;
an output data register, connected to said reduced data generator and said number-of-carries encoding circuit for receiving the output data from said reduced data generator and for shifting said output data by the number of carry signals represented by the carry code from said number-of-carries encoding circuit;
a selector, connected to said output data register, for selecting succeeding n bits;
and
a zone position generator, responsive to said number-of-carries encoding circuit, for generating zone position information representing a zone position of n-bit data in said output data register to be selected by said selector, and which is defined by the code of the number of carry signals generated from said number-of-carries encoding circuit.

12 more elements

An image size converter which receives input dot pattern data, for enlarging or reducing the image size of the input dot pattern data in accordance with a scale value, comprising:

means for inputting the scale value to the image size converter;
means for receiving the scale value from said inputting means and for generating in parallel a plurality of carry signals;
means for receiving in parallel said plurality of carry signals and the input dot pattern data and for producing output dot pattern data;
said means for generating a plurality of carry signals including:
means for generating predetermined multiples of the scale value;
first through nth adders, each of which receives predetermined ones of the multiples of the scale value at a first input thereof, n being an integer of 2 or more;
a register for holding an output sum from said nth adder and supplying the output sum to a second input of each of said first through nth adders, a content of said register being updated for each of predetermined sets of input dot pattern data;
first through (n-1)th noncoincidence detecting means, each connected between an adjacent two adders, for detecting noncoincidence between a least significant bit of each sum from said second through nth adders and of said first through (n-1)th adders, respectively, and for generating said plurality of carry signals;
and wherein said first adder outputs a carry signal of logic "1" representing a carry from a fraction part to an integer part during an addition by said first adder, said first through (n-1)th noncoincidence detecting means upon detecting noncoincidence outputting a carry signal of logic "1", and said means for producing output adopt pattern data comprising an image size reduction data generator which includes:
a reduced data generator which receives n-bit input dot pattern data and receives an addition result of said first adder and detection results of said first through (n-1)th noncoincidence detecting means in a one-to-one correspondence manner, and said reduced data generator thinning out the dot pattern data until detecting the carry signal of logic "1" from said first adder or said first through (n-1)th noncoincidence detecting means;
a number-of-carries encoding circuit for receiving the carry signals and generating a carry code representing the number of carry signals;
an output data register, connected to said reduced data generator and said number-of-carries encoding circuit for receiving the output data from said reduced data generator and for shifting said output data by the number of carry signals represented by the carry code from said number-of-carries encoding circuit;
a selector, connected to said output data register, for selecting succeeding n bits;
and
a zone position generator responsive to said number-of-carries encoding circuit, for generating zone position information which represents a zone position of n-bit data in said output data register to be selected by said selector, and which is defined by the code of the number of carry signals generated from said number-of-carries encoding circuit.

12 more elements

An image size converter which receives input dot pattern for enlarging or reducing the image size of the input dot pattern data in accordance with a scale value, comprising:

means for inputting the scale value to the image size converter;
means for receiving the scale value from said inputting means and for generating in parallel a plurality of carry signals;
said means for generating a plurality of carry signals comprising:
means for generating predetermined multiples of the scale value;
first through nth adders, each of which receives one of said predetermined multiples of the scale value at a first input thereof, n being an integer of 2 or more, said first adder outputting a carry signal of logic "1" representing a carry from a fraction part to an integer part during an addition by said first adder;
a register for holding an output sum from said nth adder and supplying the output to a second input of each of said first through nth adders, a content of said register being updated for each of predetermined sets of input dot pattern data;
first through (n-1)th noncoincidence detecting means, each connected between an adjacent two adders, for detecting noncoincidence between a least significant bit of each sum from said second through nth adders and of said first through (n-1)th adders, respectively, each of said first through (n-1)th noncoincidence detecting means outputting a carry signal of logic "1" upon detecting noncoincidence;
means for receiving in parallel said plurality of carry signals and the input dot pattern data and for producing output dot pattern data, said means for producing an output dot pattern comprising an image size enlargement data generator which includes:
an input register for receiving an n-bit image enlargement object dot data;
a selector, connected to said input register, for selecting succeeding n-bit data from said input register;
a number-of-carries encoding circuit for receiving the carry signals and generating a carry code representing a number of carry signals;
a zone position generator, connected to said selector, for generating zone position information which represents bit positions of n-bit data held in said input register to be selected by said selector, and which is defined by the code of the number of carry signals generated from said number-of-carries encoding circuit;
and
an enlargement data generator, connected to said selector, said first adder, and said first through (n-1)th noncoincidence detecting means, for coping the respective dots of the data output from said selector until detecting the carry signal of logic "1" from said first adder and said first through (n-1)th noncoincidence detecting means.

11 more elements

An image size converter which receives input dot pattern data from enlarging or reducing the image size in accordance with a scale value, comprising:

means for inputting the scale value to the image size converter;
means, operatively coupled to said inputting means, for receiving said scale value and for generating in parallel a plurality of carry signals, said means for generating a plurality of carry signals comprising:
means for generating predetermined multiples of the scale value;
first through nth adders each of which receives one of said predetermined multiples of the scale value at a first input, n being an integer of 2 or more, said first adder outputting a carry signal of logic "1" representing a carry from a fraction part to an integer part during an addition by said first adder;
a register for holding an output from said nth adder and for supplying the output to a second input of each of said first through nth adders, a content of said register being updated for each of predetermined sets of input dot pattern data;
first through (n-1)th noncoincidence detecting means, each connected between an adjacent two adders, for detecting noncoincidence between least significant bits of integer parts of the respective sums from said second through nth adders and of said first through (n-1)th adders;
said first through (n-1)th noncoincidence detecting means upon detecting noncoincidence outputting a carry signal of logic "1";
means for receiving and processing the input dot pattern data and for generating output dot pattern data, said means for generating output dot pattern data comprising an image size reduction data generator including:
a reduced data generator which receives n-bit input dot pattern data and receives an addition result of said first adder and detection results of said first through (n-1)th noncoincidence detecting means in a one-to-one correspondence manner, and said reduced data generator including means for ORing the input dot pattern data in accordance with occurrence of the carry signal of logic "1" from said first adder or first through (n-1)th noncoincidence detecting means;
and
means for controlling the processing of the image pattern data in response to parallel input of said carry signals to modify the output dot pattern data in accordance with the scale value, said means for controlling the processing of the image pattern comprising:
a number-of-carries encoding circuit for receiving the carry signals and generating a carry code representing the number of carry signals;
an output data register, connected to said reduced data generator and said number-of-carries encoding circuit, for receiving output data from said reduced data generator and for shifting said output data by the number of carry signals represented by the carry code from said number-of-carries encoding circuit;
a selector, connected to said output data register, for selecting succeeding n bits;
and
a zone position generator, connected to said number-of-carries encoding circuit, for generating zone position information representing a zone position of n-bit data to be selected by said selector, and which is defined by the code of the number of carry signals generated from said number-of-carries encoding circuit.

13 more elements

An image size converter which receives input dot pattern data for enlarging or reducing the image size in accordance with a scale value, comprising:

means for inputting the scale value to the image size converter;
means, operatively coupled to said inputting means, for receiving said scale value and for generating in parallel a plurality of carry signals, said means for generating a plurality of carry signals comprising:
means for generating predetermined multiples of the scale value;
first through nth adders each of which receives one of said predetermined multiples of the scale value at a first input, n being an integer of 2 or more, said first adder outputting a carry of logic "1" representing a carry from a fraction part to an integer part during an addition by said first adder;
a register for holding an output from said nth adder and for supplying the output to a second input of each of said first through nth adders, a content of said register being updated for each of predetermined sets of input dot pattern data;
and
first through (n-1)th noncoincidence detecting means, each connected between an adjacent two adders, for detecting noncoincidence between a least significant bit of each sum from said second through nth adders and of said first through (n-1)th adders, respectively, and for outputting a carry signal of logic "1" upon detecting noncoincidence;
means for receiving and processing the input dot pattern data and for generating output dot pattern data, said means for generating output dot pattern data comprising an image size reduction data generator which includes:
a reduced data generator which receives a pattern input of n bits and receives an addition result of said first adder and detection results of said first through (n-1)th noncoincidence detecting means in a one-to-one correspondence manner, and said reduced data generator thinning out the input dot pattern data until detecting the carry signal of logic "1" from said first adder or said first through (n-1)th noncoincidence detecting means;
and
means for controlling the processing of the image pattern data in response to parallel input of said carry signals to modify the output dot pattern data in accordance with the scale value, said means for controlling the processing of the image pattern data comprising:
a number-of-carries encoding circuit for receiving the carry signals and generating a carry code representing the number of carry signals;
an output data register, connected to said reduced data generator and said number-of-carries encoding circuit, for receiving output data from said reduced data generator and for shifting said output data by the number of carry signals represented by the carry code from the number-of-carries encoding circuit;
a selector, connected to said output data register, for selecting succeeding n bits;
and
a zone position generator, connected to said number-of-carries encoding circuit, for generating zone position information representing a zone position of n-bit data in said output data register to be selected by said selector, and which is defined by the code of the number of carry signals generated from said number-of-carries encoding circuit.

13 more elements

An image size converter which receives input dot pattern data for enlarging or reducing the image size in accordance with a scale value, comprising:

means for inputting the scale value to the image size converter;
means, operatively coupled to said inputting means, for receiving the scale value and for generating in parallel a plurality of carry signals, said means for generating a plurality of carry signals comprising:
means for generating predetermined multiples of the scale value;
first through nth adders each of which receives one of said predetermined multiples of the scale value at a first input, said first adder outputting a carry signal of logic "1" representing a carry from a fraction part to an integer part during an addition by said first adder;
a register for holding an output from said nth adder and for supplying the output to a second input of each of said first through nth adders, a content of said register being updated for each of predetermined sets of input dot pattern data;
and
first through (n-1)th noncoincidence detecting means, each connected between an adjacent two adders, for detecting noncoincidence between a least significant bit of each sum from said second through nth adders and of said first through (n-1)th adders, respectively, each of said first through (n-1)th noncoincidence detecting means outputting a carry signal of logic "1" upon detecting noncoincidence;
means for receiving and processing the input dot pattern data and for generating output dot pattern data, said means for generating output dot pattern data comprising an image size enlargement data generator which includes:
an input register for receiving n-bit image enlargement object dot data;
a selector, connected to said input register, for selecting succeeding n-bit data from said input register;
and
an enlargement data generator, connected to said selector, said first adder, and said first through (n-1)th noncoincidence detecting means, for copying the respective dots of the data output from said selector until detecting the carry signal of logic "1" from said first adder and said first through (n-1)th noncoincidence detecting means;
and
means for controlling the processing of the image pattern data in response to parallel input of said carry signals to modify the output dot pattern data in accordance with the scale value, said means for controlling comprising:
a number-of-carries encoding circuit for receiving the carry signals and generating a carry code representing a number of carry signals;
and
a zone position generator, connected to said selector, for generating zone position information which represents bit positions of n-bit data held in said input register to be selected by said selector, and which is defined by the code of the number of carry signals generated from said number-of-carries encoding circuit.

14 more elements

Dependencies are inferred from the claim text.

Image size converter

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Image size converter

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Abstract

Claims51