Lead frame and electronic divice

An electronic device comprising:

• a semiconductor chip;
• a plurality of leads arranged around said chip supporting means, each of said plurality of leads having an inner end disposed proximate to said chip supporting means;
• said chip being secured to said chip supporting means;
• wires electrically connected said leads and said chip;
• and
• sealing means sealing said leads, said chip supporting means and said wires;
• said inner end of at least one of said plurality of leads including a first lead portion extending toward said chip supporting means in a direction substantially perpendicular to said chip supporting means, a second lead portion contiguous with said first lead portion, said second lead portion extending in a direction away from said chip supporting means, and a third lead portion connected between said first lead portion and said second lead portion, said third lead portion being contiguous with said first and second lead portions and having a first end connected to said first lead portion and a second end connected to said second lead portion, said second lead portion having an end portion which is the end of said inner end of said at least one of said plurality of leads, a part of at least one of said second lead portion and said third lead portion being disposed at a position between a peripheral wall of said chip supporting means and a first end of an adjacent lead of said plurality of leads, one of said wires being electrically connected between said second lead portion and a wire bonding space on said chip.

A lead frame comprising:

• chip supporting means for supporting a chip;
• and
• a plurality of leads arranged around said chip supporting means, each of said plurality of leads having an inner end disposed proximate to said chip supporting means;
• said inner end of at least one of said plurality of leads including a first lead portion extending in a direction toward said chip supporting means, said first lead portion including a part extending in a direction substantially perpendicular to said chip supporting means, a second lead portion contiguous with said first lead portion, said second lead portion extending in a direction away from said chip supporting means, and a third lead portion connected between said first lead portion and said second lead portion, said third lead portion being contiguous with said first and second lead portions and having a first end connected to said first lead portion and a second end connected to said second lead portion, said third lead portion having substantially parallel sides extending between said first and second ends thereof, one of said substantially parallel sides being disposed adjacent to and spaced a predetermined distance from a peripheral wall of said chip supporting means facing said first lead portion and extending in a direction substantially parallel with said peripheral wall, said second lead portion extending from said second end of said third lead portion in a direction away from said chip supporting means so as to have an end part thereof disposed at a position farther away from said peripheral wall of said chip supporting means than the other of said substantially parallel sides of said third lead portion, said second lead portion having an end portion which is the end of said inner end of said at least one of said plurality of leads, a part of at least one of said second lead portion and said third lead portion being disposed at a position between said peripheral wall of said chip supporting means and a part of a first lead portion of an adjacent lead of said plurality of leads extending in a direction toward and substantially perpendicular to said chip supporting means.

An electronic device comprising:

• a semiconductor chip;
• a plurality of leads arranged around said chip supporting means, each of said plurality of leads having an inner end disposed proximate to said chip supporting means;
• said chip being secured to said chip supporting means;
• wires electrically connecting said leads and said chip;
• and
• sealing means sealing said leads, said chip supporting means and said wires;
• said inner end of at least one of said plurality of leads including a first lead portion extending in a direction toward said chip supporting means, said first lead portion including a part extending in a direction substantially perpendicular to said chip supporting means, a second lead portion contiguous with said first lead portion, said second lead portion extending in a direction away from said chip supporting means, and a third lead portion connected between said first lead portion and said second lead portion, said third lead portion being contiguous with said first and second lead portions and having a first end connected to said first lead portion and a second end connected to said second lead portion, said third lead portion having substantially parallel sides extending between said first and second ends thereof, one of said substantially parallel sides being disposed adjacent to and spaced a predetermined distance from a peripheral wall of said chip supporting means facing said first lead portion and extending in a direction substantially parallel with said peripheral wall, said second lead portion extending from said second end of said third lead portion in a direction away from said chip supporting means so as to have an end part thereof disposed at a position farther away from said peripheral wall of said chip supporting means than the other of said substantially parallel sides of said third lead portion, said second lead portion having an end portion which is the end of said inner end of said at least one of said plurality of leads, a part of at least one of said second lead portion and said third lead portion being disposed at a position between said peripheral wall of said chip supporting means and a part of a first lead portion of an adjacent lead of said plurality of leads extending in a direction toward and substantially perpendicular to said chip supporting means, one of said wires being electrically connected between said second lead portion and a wire bonding space on said chip.