Delayed-action motor control circuit for reducing load current

Abstract

A head drive motor operating circuit comprises a first delay circuit for generating a first pulse of duration T1 in response to an end-of-seek pulse which is generated by a control circuit. A second delay circuit is provided for generating a second pulse of duration T2 in response to the seek command input pulse if it occurs in the presence of the first pulse and for generating a seek command output pulse for application to the motor and at the end of the second pulse or in response to the seek command input pulse if it occurs in the absence of the first pulse. A seek inhibit signal is generated during an interval between the seek command output pulse and a subsequent end-of-seek pulse and applied to the control circuit to prevent it from initiating the next seek. If a seek command input pulse is generated immediately following an end-of-seek pulse, a delay time of at least T2 is therefore introduced to the application of a seek command output pulse to the motor, reducing the amount of currents to be supplied to the motor for a given interval of time.

Dependencies are inferred from the claim text.