Point synchronization generating circuit for television display and its use for symbol incrustation
AssigneeThomson-CSF
InventorsGillet Claude, Voisin Gerard, Xavier Maitre
Life of this patent
Estimating the term…
Abstract
The circuit disclosed provides for operation in wide ranges of temperature with high temporal stability. It comprises a quartz clock providing the point frequency, a delay circuit with N outputs to delay the clock signal by 1 to N increments with a value 1/NFP from one output to the following one. A decoding and control logic circuit receives the N shifted signals ad the external line synchronization and codifies the rank of the first shifted signal which follows the line synchronization. A selection logic circuit controlled by this information on rank selects the corresponding output.
Claims2
A point synchronization generating circuit for a video picture scanned line by line at a line synchronization rate indicated by a line synchronization signal corresponding to a television standard used, said circuit comprising:
- a quartz circuit producing a clock signal with a frequency corresponding to a point frequency FP of said standard;
- a delay circuit with N outputs, to delay the clock signal by 1 through N increments, with a value 1/N.multidot.FP, successively from one of said N outputs to the next;
- a memory for storing states of the N delayed clock signals at a reference instant of reception of said line synchronization signal;
- a transcoder, to convert the stored states into a ranked binary word codifying a rank of a first clock signal which follows said line synchronization signal;
- a selection logic circuit, to select one of the N delayed clock signals, under the control of a selection binary word;
- and
- a fast comparator, to compare said ranked binary word with the selection binary word used during the preceding line scanning, and to determine a new selection binary word, for a next line scanning.
Dependencies are inferred from the claim text.