Semiconductor wafer-scale integrated device composed of interconnected multiple chips each having an integration circuit chip formed thereon

A semiconductor wafer-scale integrated device including interconnected multiple semiconductor chips on each of which an integrated circuit (IC) is fabricated, comprising:

• a plurality of integrated circuit chips, each of said integrated circuit chips having a first electrically conductive layer wiring formed on each chip, and first terminal pads formed thereon, a passivation film being formed on said first conductive layer-wiring;
• a substrate composed substantially of silicon having said integrated circuit chips installed on an upper surface, gaps being formed between said integrated circuit chips;
• a binder material, formed in said gaps between said plurality of integrated circuit chips, for binding said plurality of integrated circuit chips to said substrate and to each other, said binder material being substantially coplanar with said integrated circuit chips and formed of a material selected from a group consisting of monocrystalline silicon, grown polycrystalline silicon, and grown amorphous silicon;
• a first electrically insulating layer, formed on said first electrically conductive layer-wiring and said filled gaps, except where said first terminal pads are located;
• a second electrically conductive layer-wiring, formed on said first electrically insulating layer, for operatively interconnecting one of said first terminal pads to another corresponding one of said first terminal pads;
• and
• a second terminal pad of said second electrically conductive layer-wiring being formed on said first electrically insulating layer and operatively connected to an external circuit.